Inventor

Jeffry D. Yetter

Inventor

Loveland, CO, US

Overview

20→

Patents

1993–2015

Patent span

Physics

Primary field (CPC G)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing35%

H03KPulse technique23%

G11CStatic stores12%

H04BTransmission12%

G02BOptical elements, systems or apparatus8%

H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light8%

G05FSystems for regulating electric or magnetic variables4%

PatentTitleYear

9,142,938'Apparatus and method of establishing optical communication channels between a steerable array of laser emitters and an array of optical detectors'2015 7,816,975'Circuit and method for bias voltage generation'2010 7,719,380'AC coupling circuit'2010 7,653,108'Apparatus and method of establishing optical communication channels between a steerable array of laser emitters and an array of optical detectors'2010 7,623,783'System and method of self-configuring optical communication channels between arrays of emitters and detectors'2009 7,623,793'System and method of configuring fiber optic communication channels between arrays of emitters and detectors'2009 7,269,321'System and method of configuring fiber optic communication channels between arrays of emitters and detectors'2007 7,229,218'Apparatus and method of providing an optical connection between PC boards for optical communication'2007 5,900,766'Coupling charge compensation device for VLSI circuits'1999 5,875,121'Register selection system and method'1999 5,765,209'Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages'1998 5,689,228'Parallel magnitude comparison using manchester carry chains'1997 5,434,520'Clocking systems and methods for pipelined self-timed dynamic logic circuits'1995 5,392,423'Universal pipeline latch for mousetrap logic circuits'1995 5,389,835'Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression'1995 5,329,176'Self-timed clocking system and method for self-timed dynamic logic circuits'1994 5,317,204'Mitigating the adverse effects of charge sharing in dynamic logic circuits'1994 5,299,158'Memory device with multiple read ports'1994 5,289,403'Self-timed content addressable memory access mechanism with built-in margin test feature'1994 5,208,490'Functionally complete family of self-timed dynamic logic circuits'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–1999Patents assigned to HEWLETT PACKARD CO (12)· patent assignee history

1993–1998Based in Fort Collins, CO, US· patent location history

1997–2015Based in Loveland, CO, US· patent location history

2007–2015Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (8)· patent assignee history

2015Patents assigned to FENWICK DAVID MARTIN (1)· patent assignee history

2015Patents assigned to LUEBS RICHARD JOHN (1)· patent assignee history

2015Patents assigned to MORRIS TERREL L (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HEWLETT PACKARD CO	12	1993–1999
HEWLETT PACKARD DEVELOPMENT CO	8	2007–2015
FENWICK DAVID MARTIN	1	2015
LUEBS RICHARD JOHN	1	2015
MORRIS TERREL L	1	2015

Locations

Location	Patents	Span
Loveland, CO, US	11	1997–2015
Fort Collins, CO, US	9	1993–1998