Inventor
Marcel A. Kossel
Inventor
Reichenburg, CH
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique21%
H04LTransmission of digital information, e.g. telegraphic communication19%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%
H04BTransmission8%
G01RMeasuring electric variables5%
G06FElectric digital data processing5%
G11CStatic stores5%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner5%
H03MCoding5%
H03FAmplifiers4%
PatentTitleYear
11,095,487Operating a wireline receiver with a tunable timing characteristic202111,057,039Clock divider with quadrature error correction202110,943,653Memory receiver with resistive voltage divider202110,720,994PAM-4 transmitter precoder for 1+0.5D PR channels202010,680,860Method and apparatus for generating a multi-level pseudo-random test signal202010,541,691Bang-bang phase detectors202010,454,723Decision feedback equalizer201910,256,845Symbol timing recovery based on speculative tentative symbol decisions201910,237,098Method and apparatus for generating a multi-level pseudo-random test signal201910,205,525PAM-4 transmitter precoder for 1+0.5D PR channels201910,078,342Low dropout voltage regulator with variable load compensation20189,991,990Sequence detection20189,928,035'Multiply-and-accumulate unit in carry-save adder format and application in a feedback loop equalizer'20189,882,752'Method and apparatus for generating a multi-level pseudo-random test signal'20189,762,183'Voltage-controlled ring oscillator with delay line'20179,673,805'Leakage current reduction in stacked field-effect transistors'20179,590,597'Voltage-controlled ring oscillator with delay line'20179,496,008'Determination of a common mode voltage'20169,020,021'Precoding loss reduction'20159,009,520'Closed-loop multiphase slew rate controller for signal drive in a computer system'20158,981,831'Level shifter with built-in logic function for reduced delay'20158,717,138'Inductor combining primary and secondary coils with phase shifting'20148,692,600'Multi-protocol driver slew rate calibration system for calibration slew rate control signal values'20148,686,776'Phase rotator based on voltage referencing'20148,674,737'Clock feathered slew rate control system'20148,638,149'Equalized rise and fall slew rates for a buffer'20148,519,761'Closed-loop slew-rate control for phase interpolator optimization'20138,520,724'Pipelining and sub-rate operation for memory links'20138,466,722'Startup and protection circuitry for thin oxide output stage'20138,428,110'Pipelining and sub-rate operation for memory links'20138,421,573'Inductor combining primary and secondary coils with phase shifting'20138,164,373'Drive strength control of phase rotators'20128,044,732'Continuously tunable inductor and method to continuously tune an inductor'20118,018,312'Inductor and method of operating an inductor by combining primary and secondary coils with coupling structures'20118,004,441'Small-area digital to analog converter based on master-slave configuration'20117,839,221'Phase locked loop and method for adjusting the frequency and phase in the phase locked loop'20107,783,439'Signal generator device and data eye scan system'20107,541,855'CML delay cell with linear rail-to-rail tuning range and constant output swing'20097,512,177'Method and apparatus for generating random jitter'20097,479,839'Varactor bank switching based on negative control voltage generation'20097,403,057'CML delay cell with linear rail-to-rail tuning range and constant output swing'20087,403,073'Phase locked loop and method for adjusting the frequency and phase in the phase locked loop'20087,378,885'Multiphase divider for P-PLL based serial link receivers'20087,323,913'Multiphase divider for P-PLL based serial link receivers'20087,295,604'Method for determining jitter of a signal in a serial link and high speed serial link'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2021Patents assigned to IBM (45)· patent assignee history
2007–2009Based in Zurich, CH· patent location history
2008–2021Based in Reichenburg, CH· patent location history
2011Based in Rüschlikon, CH· patent location history
2012–2015Patents assigned to KOSSEL MARCEL A (11)· patent assignee history
2012–2015Patents assigned to LIM DAIHYUN (6)· patent assignee history
2013–2015Patents assigned to THIAGARAJAN PRADEEP (5)· patent assignee history
2013–2014Patents assigned to TOIFL THOMAS H (3)· patent assignee history
2013–2020Based in Rueschlikon, CH· patent location history
2015Based in Ruesclikon, CH· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 45 | 2007–2021 |
| KOSSEL MARCEL Aself | 11 | 2012–2015 |
| LIM DAIHYUN | 6 | 2012–2015 |
| THIAGARAJAN PRADEEP | 5 | 2013–2015 |
| TOIFL THOMAS H | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Reichenburg, CH | 35 | 2008–2021 |
| Rueschlikon, CH | 6 | 2013–2020 |
| Zurich, CH | 2 | 2007–2009 |
| Ruesclikon, CH | 1 | 2015 |
| Rüschlikon, CH | 1 | 2011 |