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Inventor

Gary M. Lee

Inventor
Belmont, CA, US

Overview

21→
Patents
1988–2011
Patent span
Chemistry
Primary field (CPC C)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

C07Dprimary
C07DHeterocyclic compounds26%
C07CAcyclic or carbocyclic compounds21%
C07BGeneral methods of organic chemistry9%
A61PSpecific therapeutic activity of chemical compounds or medicinal preparations7%
H03KPulse technique7%
H04JMultiplex communication7%
H04LTransmission of digital information, e.g. telegraphic communication7%
H04QSelecting7%
B82YSpecific uses or applications of nanostructures2%
E03CDomestic plumbing installations for fresh water or waste water2%
PatentTitleYear
7,893,276'Process for preparing triazolones'20117,745,634'Process for preparing triazolones'20107,745,626'Stereoselective alkylation of chiral 2-methyl-4-protected piperazines'20107,534,884'Preparation of pharmaceutical salts'20097,133,233'Disk drive with read while write capability'20066,992,189'Synthesis of piperidine and piperazine compounds as CCR5 antagonists'20066,943,251'Preparation of salts of 4-[4-[(1R)-[4-(trifluoromethyl)phenyl]-2-methoxyethyl]-(3S)-methyl-1-piperazinyl]-4-methyl-1-[(4,6-dimethyl-5-pyrimidinyl)carbonyl] '20056,872,826'Stereoselective alkylation of chiral 2-methyl-4-protected piperazines'20056,801,518'High speed cross point switch routing circuit with word-synchronous serial back plane'20046,700,886'High speed cross point switch routing circuit with word-synchronous serial back plane'20046,377,575'High speed cross point switch routing circuit with word-synchronous serial back plane'20026,078,194'Logic gates for reducing power consumption of gallium arsenide integrated circuits'20005,670,666'Process for preparing intermediates for the synthesis of D1 antagonists'19975,502,186'Process for preparing intermediates for the synthesis of D1 antagonists'19965,463,051'Process for preparing benzazepine intermediates for the synthesis of D1 antagonists'19955,461,147'Process for preparing benzazepine intermediates for the synthesis of D1 antagonists'19955,353,448'Water recycling system using spent recycled water with fresh water'19945,266,727'Purification of alkyl sulfides'19934,798,978'GAAS FET logic having increased noise margin'19894,798,979'Schottky diode logic for E-mode FET/D-mode FET VLSI circuits'19894,737,837'Ring topology for an integrated circuit logic cell'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–1989Patents assigned to HONEYWELL INC (2)· patent assignee history
1993Patents assigned to CHEVRON RES & TECH (1)· patent assignee history
1995–2010Patents assigned to SCHERING CORP (9)· patent assignee history
1995–1997Based in Murray Hill, NJ, US· patent location history
2000–2004Patents assigned to VITESSE SEMICONDUCTOR CORP (3)· patent assignee history
2002–2004Based in Camarillo, CA, US· patent location history
2005–2011Based in Belmont, CA, US· patent location history
2005–2009Based in Oakland, CA, US· patent location history
2006Based in Fairfield, CA, US· patent location history
2010–2011Patents assigned to ROCHE PALO ALTO LLC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SCHERING CORP91995–2010
VITESSE SEMICONDUCTOR CORP32000–2004
HONEYWELL INC21988–1989
ROCHE PALO ALTO LLC22010–2011
CHEVRON RES & TECH11993
Locations
LocationPatentsSpan
Belmont, California, US52005–2011
Murray Hill, New Jersey, US41995–1997
Camarillo, California, US32002–2004
Oakland, California, US22005–2009
Fairfield, California, US12006