Inventor
Tsz-Mei Kwok
Inventor
Hsinchu, TW
Overview
Patents· 71 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H01LSemiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10BElectronic memory devices2%
C30BSingle-crystal growth1%
PatentTitleYear
11,101,347Confined source/drain epitaxy regions and method forming same202111,037,826Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same202111,031,398Structure and method for semiconductor device202110,943,790Semiconductor devices and methods for manufacturing the same202110,916,656MOS devices having epitaxy regions with reduced facets202110,879,128Semiconductor device and method of forming same202010,861,971Doping profile for strained source/drain region202010,797,173MOS devices with non-uniform p-type impurity profile202010,749,029Semiconductor device and manufacturing method thereof202010,734,520MOS devices having epitaxy regions with reduced facets202010,727,342Source and drain stressors with recessed top surfaces202010,727,229Structure and method for semiconductor device202010,714,487Semiconductor device and manufacturing method of a semiconductor device202010,546,784Semiconductor device having merged epitaxial features with arc-like bottom surface and method of making the same202010,510,753Integrated circuit and manufacturing method thereof201910,475,926MOS devices having epitaxy regions with reduced facets201910,269,577Semiconductor devices and methods for manufacturing the same201910,170,483Semiconductor device, static random access memory cell and manufacturing method of semiconductor device201910,164,096Semiconductor device and manufacturing method thereof201810,158,016MOS devices with non-uniform p-type impurity profile201810,084,089Source and drain stressors with recessed top surfaces201810,062,781MOS devices having epitaxy regions with reduced facets201810,049,936Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same201810,014,411Modulating germanium percentage in MOS devices20189,991,364Transistor strain-inducing scheme20189,922,975'Integrated circuit having field-effect trasistors with dielectric fin sidewall structures and manufacturing method thereof'20189,911,826'Devices with strained source/drain structures'20189,905,646'V-shaped epitaxially formed semiconductor layer'20189,853,155MOS devices having epitaxy regions with reduced facets20179,847,225Semiconductor device and method of manufacturing the same20179,842,910'Methods for manufacturing devices with source/drain structures'20179,825,036'Structure and method for semiconductor device'20179,806,171'Method for making source and drain regions of a MOSFET with embedded germanium-containing layers having different germanium concentration'20179,768,178'Semiconductor device, static random access memory cell and manufacturing method of semiconductor device'20179,755,077'Source and drain stressors with recessed top surfaces'20179,698,243'Transistor strain-inducing scheme'20179,691,898'Germanium profile for channel strain'20179,666,686'MOS devices having epitaxy regions with reduced facets'20179,666,691'Epitaxy profile engineering for FinFETs'20179,601,619'MOS devices with non-uniform P-type impurity profile'20179,601,574'V-shaped epitaxially formed semiconductor layer'20179,583,483'Source and drain stressors with recessed top surfaces'20179,525,026'Method of forming an epitaxial semiconductor layer in a recess and a semiconductor device having the same'20169,515,187'Controlling the shape of source/drain regions in FinFETs'20169,496,149'Semiconductor devices and methods for manufacturing the same'20169,373,695'Method for improving selectivity of epi process'20169,362,360'Modulating germanium percentage in MOS devices'20169,356,150'Method for incorporating impurity element in EPI silicon process'20169,337,337'MOS device having source and drain regions with embedded germanium-containing diffusion barrier'20169,287,398'Transistor strain-inducing scheme'20169,209,020'Method of forming an epitaxial semiconductor layer in a recess and a semiconductor device having the same'20159,209,175'MOS devices having epitaxy regions with reduced facets'20159,142,643'Method for forming epitaxial feature'20159,117,745'Mechanisms for forming stressor regions in a semiconductor device'20159,117,905'Method for incorporating impurity element in EPI silicon process'20159,076,734'Defect reduction for formation of epitaxial layer in source and drain regions'20159,012,964'Modulating germanium percentage in MOS devices'20158,975,144'Controlling the shape of source/drain regions in FinFETs'20158,853,039'Defect reduction for formation of epitaxial layer in source and drain regions'20148,835,982'Method of manufacturing strained source/drain structures'20148,815,713'Reducing pattern loading effect in epitaxy'20148,796,788'Semiconductor devices with strained source/drain structures'20148,674,453'Mechanisms for forming stressor regions in a semiconductor device'20148,652,894'Method for fabricating a FinFET device'20148,487,354'Method for improving selectivity of epi process'20138,362,575'Controlling the shape of source/drain regions in FinFETs'20138,343,872'Method of forming strained structures with compound profiles in semiconductor devices'20138,310,013'Method of fabricating a FinFET device'20128,278,196'High surface dopant concentration semiconductor device and method of fabricating'20128,263,451'Epitaxy profile engineering for FinFETs'20128,264,021'Finfets and methods for forming the same'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (25)· patent assignee history
2012–2017Patents assigned to KWOK TSZ-MEI (13)· patent assignee history
2012–2017Patents assigned to LIN HSIEN-HSIN (9)· patent assignee history
2012–2017Patents assigned to CHEN KUAN-YU (8)· patent assignee history
2012–2021Based in Hsinchu, TW· patent location history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (46)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 46 | 2016–2021 |
| TAIWAN SEMICONDUCTOR MFG | 25 | 2012–2016 |
| KWOK TSZ-MEIself | 13 | 2012–2017 |
| LIN HSIEN-HSIN | 9 | 2012–2017 |
| CHEN KUAN-YU | 8 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 71 | 2012–2021 |