Inventor
Sara S. Baghsorkhi
Inventor
San Jose, CA, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing41%
G06NComputing arrangements based on specific computational models20%
G06TImage data processing or generation, in general19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H04LTransmission of digital information, e.g. telegraphic communication3%
G06KGraphical data reading2%
G06VImage or video recognition or understanding1%
G09GArrangements or circuits for control of indicating devices using static means to present variable information1%
H04WWireless communication networks1%
PatentTitleYear
11,074,072Compute optimizations for neural networks using bipolar binary weight202111,049,213Efficient sharing and compression expansion of data across processing systems202110,956,330Extend GPU/CPU coherency to multi-GPU cores202110,929,749Neural network optimization mechanism202110,902,547Compute optimization mechanism for deep neural networks202110,891,707Coordination and increased utilization of graphics processors during inference202110,853,906Compute optimizations for low precision machine learning operations202010,824,938Specialized fixed function hardware for efficient convolution202010,802,942Methods and apparatus to detect anomalies of a monitored system202010,769,748Programmable coarse grained and sparse matrix compute hardware with advanced scheduling202010,726,514Compute optimizations for low precision machine learning operations202010,521,349Extend GPU/CPU coherency to multi-GPU cores201910,497,084Efficient sharing and compression expansion of data across processing systems201910,417,731Compute optimization mechanism for deep neural networks201910,417,734Compute optimization mechanism for deep neural networks201910,409,603Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory201910,410,098Compute optimizations for neural networks201910,402,177Methods and systems to vectorize scalar computer program loops having loop-carried dependences201910,372,450Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate201910,324,768Lightweight restricted transactional memory for speculative compiler optimization201910,304,154Coordination and increased utilization of graphics processors during inference201910,261,903Extend GPU/CPU coherency to multi-GPU cores201910,248,422Systems, apparatuses, and methods for snooping persistent memory store addresses201910,242,423Compute optimizations for low precision machine learning operations201910,186,011Programmable coarse grained and sparse matrix compute hardware with advanced scheduling201910,025,570Modifying applications for incremental checkpoints20189,921,832'Instruction to reduce elements in a vector register with strided access pattern'20189,921,841'System and method for executing an instruction to permute a mask'20189,910,650'Method and apparatus for approximating detection of overlaps between memory ranges'20189,898,266'Loop vectorization methods and apparatus'20189,798,541'Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register'20179,733,913'Methods and systems to vectorize scalar computer program loops having loop-carried dependences'20179,720,667'Automatic loop vectorization using hardware transactional memory'20179,710,279'Method and apparatus for speculative vectorization'20179,703,558'Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate'20179,690,582'Instruction and logic for cache-based speculative vectorization'20179,690,360'Technologies for discontinuous execution by energy harvesting devices'20179,588,814'Fast approximate conflict detection'20179,268,541'Methods and systems to vectorize scalar computer program loops having loop-carried dependences'20169,268,626'Apparatus and method for vectorization with speculation support'20169,244,677'Loop vectorization methods and apparatus'20169,189,236'Speculative non-faulting loads and gathers'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to INTEL CORP (42)· patent assignee history
2015–2017Patents assigned to HARTONO ALBERT (5)· patent assignee history
2015–2017Patents assigned to VASUDEVAN NALINI (5)· patent assignee history
2015–2017Patents assigned to BHARADWAJ JAYASHANKAR (4)· patent assignee history
2015–2017Patents assigned to LEE VICTOR W (4)· patent assignee history
2015–2021Based in San Jose, CA, US· patent location history
2020Based in Los Gatos, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 42 | 2015–2021 |
| HARTONO ALBERT | 5 | 2015–2017 |
| VASUDEVAN NALINI | 5 | 2015–2017 |
| BHARADWAJ JAYASHANKAR | 4 | 2015–2017 |
| LEE VICTOR W | 4 | 2015–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 41 | 2015–2021 |
| Los Gatos, California, US | 1 | 2020 |