Inventor
Hong-Yi Chen
Inventor
Fremont, CA, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing47%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
G11CStatic stores12%
G11BInformation storage based on relative movement between record carrier and transducer5%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
B01DSeparation1%
B08BCleaning in general1%
B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool1%
C12MApparatus for enzymology or microbiology1%
PatentTitleYear
9,765,444'Continuous electrochemical machining apparatus'20179,608,541'DC-to-AC conversion apparatus and method of operating the same'20179,306,474'Power conversion system and method of operating the same'20169,158,355'Dynamic core switching'20159,090,864'Multi-tube biofilter system for treating waste gas'20158,935,591'System and method to correct errors in data read from a source supplying streaming data'20158,909,903'Providing data to registers between execution stages'20148,874,948'Apparatuses for operating, during respective power modes, transistors of multiple processors at corresponding duty cycles'20148,806,181'Dynamic pipeline reconfiguration including changing a number of stages'20148,667,370'Systems and methods for arbitrating use of processor memory'20148,621,152'Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access'20138,572,416'Low power computer with main and auxiliary processors'20138,526,257'Processor with memory delayed bit line precharging'20138,468,324'Dual thread processor'20138,392,799'Systems and methods for arbitrating use of processor memory'20138,347,034'Transparent level 2 cache that uses independent tag and valid random access memory arrays for cache access'20138,295,110'Processor instruction cache with dual-read modes'20128,195,922'System for dynamically allocating processing time to multiple threads'20128,176,386'Systems and methods for processing streaming data'20128,089,823'Processor instruction cache with dual-read modes'20128,078,828'Memory mapped register file'20118,074,056'Variable length pipeline processor architecture'20118,027,218'Processor instruction cache with dual-read modes'20117,949,833'Transparent level 2 cache controller'20117,882,332'Memory mapped register file'20117,827,423'Low power computer with main and auxiliary processors'20107,787,324'Processor instruction cache with dual-read modes'20107,788,514'Low power computer with main and auxiliary processors'20107,730,335'Low power computer with main and auxiliary processors'20107,730,285'Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof'20107,685,372'Transparent level 2 cache controller'20107,668,356'Automatic determination of joint space width from hand radiographs'20107,568,083'Memory mapped register file and method for accessing the same'20097,558,942'Memory mapped register file and method for accessing the same'20097,437,532'Memory mapped register file'20087,096,345'Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof'20066,816,943'Scratch pad memories'20046,676,770'Apparatus and method for removing particles from wafer pods'20046,643,736'Scratch pad memories'20036,473,864'Method and system for providing power management to a processing system'20026,356,995'Microcode scalable processor'20025,926,841'Segment descriptor cache for a processor'19995,864,372'Apparatus for implementing a block matching algorithm for motion estimation in video image processing'19995,828,590'Multiplier based on a variable radix multiplier coding'19985,809,522'Microprocessor system with process identification tag entries to reduce cache flushing after a context switch'19985,793,659'Method of modular reduction and modular reduction circuit'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2015Based in Fremont, CA, US· patent location history
1998–1999Based in Beijing, CN· patent location history
2006–2015Patents assigned to MARVELL INT LTD (18)· patent assignee history
2010–2015Patents assigned to MARVELL WORLD TRADE LTD (13)· patent assignee history
2011–2015Patents assigned to CHEN HONG-YI (13)· patent assignee history
2011–2014Patents assigned to TJENG JENSEN (4)· patent assignee history
2012–2015Patents assigned to SUTARDJA SEHAT (6)· patent assignee history
2013–2015Based in Los Altos Hills, CA, US· patent location history
2016–2017Based in Taoyuan County, TW· patent location history
2017Based in Taichung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 18 | 2006–2015 |
| CHEN HONG-YIself | 13 | 2011–2015 |
| MARVELL WORLD TRADE LTD | 13 | 2010–2015 |
| SUTARDJA SEHAT | 6 | 2012–2015 |
| TJENG JENSEN | 4 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 33 | 1998–2015 |
| Los Altos Hills, California, US | 4 | 2013–2015 |
| Beijing, CN | 3 | 1998–1999 |
| Taoyuan County, TW | 2 | 2016–2017 |
| Taichung, TW | 1 | 2017 |