Inventor

Songsu Cho

Inventor

Ibaraki, JP

Overview

1993–2005

Patent span

Electricity

Primary field (CPC H)

Patents· 13 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices46%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H10DInorganic electric semiconductor devices13%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%

PatentTitleYear

6,969,649'Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices'2005 6,753,219'Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices'2004 6,077,735'Method of manufacturing semiconductor device'2000 6,060,352'Method of manufacturing semiconductor device with increased focus margin'2000 6,023,084'Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same'2000 5,937,290'Method of manufacturing semiconductor integrated circuit devices using phase shifting mask'1999 5,933,724'Method of manufacturing a semiconductor integrated circuit device using a photomask in which transmitted light beam intensities are controlled'1999 5,933,726'Method of forming a semiconductor device have a screen stacked cell capacitor'1999 5,831,300'Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same'1998 5,804,479'Method for forming semiconductor integrated circuit device having a capacitor'1998 5,732,009'Semiconductor integrated circuit device including a DRAM in which a cell selection transistor has a stabilized threshold voltage'1998 5,578,849'Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance'1996 5,221,634'Method of making semiconductor device employing self diffusion of dopant from contact member for augmenting electrical connection to doped region in substrate'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2005Patents assigned to TEXAS INSTRUMENTS INC (13)· patent assignee history

1993–2005Based in Ibaraki, JP· patent location history

1996–2004Patents assigned to HITACHI LTD (9)· patent assignee history

1998–2000Based in Fujishiro, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TEXAS INSTRUMENTS INC	13	1993–2005
HITACHI LTD	9	1996–2004

Locations

Location	Patents	Span
Ibaraki, JP	10	1993–2005
Fujishiro, JP	3	1998–2000