Inventor
Katsuhiro Kitagawa
Inventor
Tokyo, JP
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique36%
G11CStatic stores29%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses29%
G06FElectric digital data processing2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data2%
PatentTitleYear
10,937,473Clock signal drivers for read and write memory operations202110,840,910Apparatuses and methods for level shifting202010,803,923Apparatuses and methods for providing clock signals in a semiconductor device202010,734,046Apparatus and methods for providing voltages to conductive lines between which clock signal lines are disposed202010,418,081Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed201910,339,998Apparatuses and methods for providing clock signals in a semiconductor device201910,218,342System and method for duty cycle correction201910,140,275Message information generating apparatus, outgoing call control apparatus, message information generating method, and outgoing call control method201810,128,847Apparatuses and methods for level shifting20189,729,131'System and method for duty cycle correction'20179,590,606'Semiconductor device having duty correction circuit'20179,559,710'Semiconductor device including oscillator'20179,472,255'Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit'20169,065,456'Semiconductor device having DLL circuit'20159,054,713'Semiconductor device generating internal clock signal having higher frequency than that of input clock signal'20158,917,127'Semiconductor device having delay line'20148,848,468'Semiconductor device and control method thereof for permitting the reception of data according to a control signal'20148,803,576'Semiconductor device having duty-cycle correction circuit'20148,760,205'Semiconductor device and input signal reception circuit'20148,713,331'Semiconductor device including a clock generating circuit for generating an internal signal having a coarse delay line, a fine delay line and a selector circuit'20148,698,535'Semiconductor device having delay line'20148,436,657'Semiconductor device having output driver'20138,299,829'Clock generation circuit, semiconductor device including the same, and method of generating clock signal'20127,932,759'DLL circuit and control method therefor'20117,876,138'DLL circuit and semiconductor device having the same'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011–2015Patents assigned to ELPIDA MEMORY INC (7)· patent assignee history
2011–2021Based in Tokyo, JP· patent location history
2012–2014Patents assigned to KITAGAWA KATSUHIRO (5)· patent assignee history
2014–2016Patents assigned to PS4 LUXCO SARL (4)· patent assignee history
2015–2021Patents assigned to MICRON TECHNOLOGY INC (12)· patent assignee history
2015Based in Toyko, JP· patent location history
2018Patents assigned to FUJITSU LTD (1)· patent assignee history
2018–2020Based in Hachioji, JP· patent location history
2018Based in Sakai, JP· patent location history
2019–2020Based in Hino, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 12 | 2015–2021 |
| ELPIDA MEMORY INC | 7 | 2011–2015 |
| KITAGAWA KATSUHIROself | 5 | 2012–2014 |
| PS4 LUXCO SARL | 4 | 2014–2016 |
| FUJITSU LTD | 1 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 16 | 2011–2021 |
| Hachioji, JP | 5 | 2018–2020 |
| Hino, JP | 2 | 2019–2020 |
| Sakai, JP | 1 | 2018 |
| Toyko, JP | 1 | 2015 |