Inventor
Ralf Lerner
Inventor
Erfurt, DE
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10DInorganic electric semiconductor devices18%
H01LSemiconductor devices14%
G06FElectric digital data processing8%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
11,037,812Method for a transfer print between substrates202110,930,497Semiconductor substrate and method for producing a semiconductor substrate202110,845,710Geometrically shaped components in an assembly for a transfer print and associated methods202010,186,502Integrated circuit having a component provided by transfer print and method for making the integrated circuit20199,070,768'DMOS transistor having an increased breakdown voltage and method for production'20158,921,945'High-voltage power transistor using SOI technology'20148,823,095'MOS-power transistors with edge termination with small area requirement'20148,793,116'Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces'20148,759,169'Method for producing silicon semiconductor wafers comprising a layer for integrating III-V semiconductor components'20148,546,207'Method for fabricating semiconductor wafers for the integration of silicon components with HEMTs, and appropriate semiconductor layer arrangement'20138,530,999'Semiconductor component with isolation trench intersections'20138,448,101'Layout method for vertical power transistors having a variable channel width'20138,278,183'Production of isolation trenches with different sidewall dopings'20128,247,884'Semiconductor structure for fabricating a handle wafer contact in a trench insulated SOI disc'20128,190,415'Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces'20128,053,897'Production of a carrier wafer contact in trench insulated integrated SOI circuits having high-voltage components'20117,989,308'Creation of dielectrically insulating soi-technlogical trenches comprising rounded edges for allowing higher voltages'20117,989,921'Soi vertical bipolar power component'20117,625,805'Passivation of deep isolating separating trenches with sunk covering layers'20097,598,098'Monitoring the reduction in thickness as material is removed from a wafer composite and test structure for monitoring removal of material'20097,588,948'Test structure for electrically verifying the depths of trench-etching in an SOI wafer, and associated working methods'20097,517,813'Two-step oxidation process for semiconductor wafers'20097,271,074'Trench insulation in substrate disks comprising logic semiconductors and power semiconductors'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2019Patents assigned to X FAB SEMICONDUCTOR FOUNDRIES (19)· patent assignee history
2007–2021Based in Erfurt, DE· patent location history
2012–2015Patents assigned to LERNER RALF (11)· patent assignee history
2012–2014Patents assigned to MIESCH WOLFGANG (3)· patent assignee history
2013–2015Patents assigned to KITTLER GABRIEL (3)· patent assignee history
2019–2021Patents assigned to X FAB SEMICONDUCTOR FOUNDRIES GMBH (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| X FAB SEMICONDUCTOR FOUNDRIES | 19 | 2007–2019 |
| LERNER RALFself | 11 | 2012–2015 |
| X FAB SEMICONDUCTOR FOUNDRIES GMBH | 4 | 2019–2021 |
| KITTLER GABRIEL | 3 | 2013–2015 |
| MIESCH WOLFGANG | 3 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Erfurt, DE | 23 | 2007–2021 |