Inventor

Chaw Sing Ho

Inventor

Singapore, SG

Overview

20→

Patents

2000–2019

Patent span

Electricity

Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices40%

B41JTypewriters15%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

H01LSemiconductor devices8%

H10BElectronic memory devices8%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

G11CStatic stores3%

H05KPrinted circuits3%

Y10TTechnical subjects covered by former us classification3%

PatentTitleYear

10,336,069Electrically-functional optical target2019 10,319,728Fluid ejection devices comprising memory cells2019 9,908,332'Ink property sensing on a printhead'2018 9,559,106'Memory cell that prevents charge loss'2017 9,457,571'Fluid ejection apparatuses including a substrate with a bulk layer and a epitaxial layer'2016 9,252,149'Device including active floating gate region area that is smaller than channel area'2016 9,199,460'Apparatuses including a plate having a recess and a corresponding protrusion to define a chamber'2015 6,902,981'Structure and process for a capacitor and other devices'2005 6,730,573'MIM and metal resistor formation at CU beol using only one extra mask'2004 6,709,918'Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology'2004 6,645,810'Method to fabricate MIM capacitor using damascene process'2003 6,624,040'Self-integrated vertical MIM capacitor in the dual damascene process'2003 6,548,367'Method to fabricate MIM capacitor with a curvillnear surface using damascene process'2003 6,528,838'Damascene MIM capacitor with a curvilinear surface structure'2003 6,410,376'Method to fabricate dual-metal CMOS transistors for sub-0.1 m ULSI integration'2002 6,410,429'Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions'2002 6,281,117'Method to form uniform silicide features'2001 6,180,501'Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process'2001 6,156,654'Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices'2000 6,010,954'Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2005Patents assigned to CHARTERED SEMICONDUCTOR MFG (11)· patent assignee history

2000–2001Patents assigned to UNIV SINGAPORE (4)· patent assignee history

2000–2019Based in Singapore, SG· patent location history

2003Patents assigned to AGILENT TECHNOLOGIES INC (2)· patent assignee history

2003Patents assigned to CHARTERED SEMICONDUCTORS MFG L (2)· patent assignee history

2015–2019Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CHARTERED SEMICONDUCTOR MFG	11	2000–2005
HEWLETT PACKARD DEVELOPMENT CO	5	2015–2019
UNIV SINGAPORE	4	2000–2001
AGILENT TECHNOLOGIES INC	2	2003
CHARTERED SEMICONDUCTORS MFG L	2	2003

Locations

Location	Patents	Span
Singapore, SG	20	2000–2019