Inventor

Richard J. Eickemeyer

Inventor

Rochester, MN, US

Overview

62→

Patents

1993–2021

Patent span

Physics

Primary field (CPC G)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing95%

H04LTransmission of digital information, e.g. telegraphic communication3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

10,942,743Splitting load hit store table for out-of-order processor2021 10,915,446Prefetch confidence and phase prediction for improving prefetch performance in bandwidth constrained scenarios2021 10,795,683Predicting indirect branches using problem branch filtering and pattern cache2020 10,725,783Splitting load hit store table for out-of-order processor2020 10,664,279Instruction prefetching in a computer processor using a prefetch prediction vector2020 10,387,162Effective address table with multiple taken branch handling for out-of-order processors2019 10,379,857Dynamic sequential instruction prefetching2019 10,353,710Techniques for predicting a target address of an indirect branch instruction2019 10,209,995Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions2019 10,191,845Prefetch performance2019 10,191,847Prefetch performance2019 10,175,987Instruction prefetching in a computer processor using a prefetch prediction vector2019 10,078,514Techniques for dynamic sequential instruction prefetching2018 10,042,647Managing a divided load reorder queue2018 9,916,245'Accessing partial cachelines in a data cache'2018 9,524,166'Tracking long GHV in high performance out-of-order superscalar processors'2016 9,465,744'Data prefetch ramp implemenation based on memory utilization'2016 9,442,736'Techniques for selecting a predicted indirect branch address from global and local caches'2016 8,856,453'Persistent prefetch data stream settings'2014 8,347,068'Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor'2013 8,261,276'Power-efficient thread priority enablement'2012 8,140,833'Implementing polymorphic branch history table reconfiguration'2012 8,140,829'Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution'2012 8,091,073'Scaling instruction intervals to identify collection points for representative instruction traces'2012 7,877,580'Branch lookahead prefetch for microprocessors'2011 7,844,928'Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information'2010 7,797,521'Method, system, and computer program product for path-correlated indirect address predictions'2010 7,707,396'Data processing system, processor and method of data processing having improved branch target address cache'2010 7,620,799'Using a modified value GPR to enhance lookahead prefetch'2009 7,594,096'Load lookahead prefetch for microprocessors'2009 7,552,318'Branch lookahead prefetch for microprocessors'2009 7,469,407'Method for resource balancing using dispatch flush in a simultaneous multithread processor'2008 7,444,498'Load lookahead prefetch for microprocessors'2008 7,421,567'Using a modified value GPR to enhance lookahead prefetch'2008 7,392,366'Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches'2008 6,988,186'Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry'2006 6,931,639'Method for implementing a variable-partitioned queue for simultaneous multithreaded processors'2005 6,922,767'System for allowing only a partial value prediction field/cache size'2005 6,697,935'Method and apparatus for selecting thread switch events in a multithreaded processor'2004 6,694,425'Selective flush of shared and other pipeline stages in a multithread processor'2004 6,567,839'Thread switch control in a multithreaded processor system'2003 6,393,552'Method and system for dividing a computer processor register into sectors'2002 6,336,160'Method and system for dividing a computer processor register into sectors and storing frequently used values therein'2002 6,105,051'Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor'2000 6,088,788'Background completion of instruction and associated fetch request in a multithread processor'2000 6,076,157'Method and apparatus to force a thread switch in a multithreaded processor'2000 6,061,710'Multithreaded processor incorporating a thread latch register for interrupt service new pending threads'2000 6,049,867'Method and system for multi-thread switching only when a cache miss occurs at a second or higher level'2000 6,021,481'Effective-to-real address cache managing apparatus and method'2000 5,940,877'Cache address generation with and without carry-in'1999 5,878,243'Apparatus for decreasing the cycle times of a data processing system'1999 5,802,564'Method and apparatus for increasing processor performance'1998 5,778,208'Flexible pipeline for interlock removal'1998 5,652,774'Method and apparatus for decreasing the cycle times of a data processing system'1997 5,651,136'System and method for increasing cache efficiency through optimized data allocation'1997 5,500,942'Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions'1996 5,459,844'Predecode instruction compounding'1995 5,448,746'System for comounding instructions in a byte stream prior to fetching and identifying the instructions for execution'1995 5,442,767'Address prediction to avoid address generation interlocks in computer systems'1995 5,377,336'Improved method to prefetch load instruction data'1994 5,355,460'In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution'1994 5,197,135'Memory management for scalable compound instruction set machines with in-memory compounding'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2021Patents assigned to IBM (61)· patent assignee history

1993–1996Based in Endicott, NY, US· patent location history

1994–1995Based in Binghamton, NY, US· patent location history

1995–2021Based in Rochester, MN, US· patent location history

2012–2013Patents assigned to EICKEMEYER RICHARD JAMES (4)· patent assignee history

2012–2014Patents assigned to EICKEMEYER RICHARD J (2)· patent assignee history

2012Patents assigned to BELL JR ROBERT H (1)· patent assignee history

2016Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	61	1993–2021
EICKEMEYER RICHARD JAMESself	4	2012–2013
EICKEMEYER RICHARD Jself	2	2012–2014
GLOBALFOUNDRIES INC	2	2016
BELL JR ROBERT H	1	2012

Locations

Location	Patents	Span
Rochester, Minnesota, US	56	1995–2021
Endicott, New York, US	4	1993–1996
Binghamton, New York, US	2	1994–1995