Inventor
Sung Kwon Kang
Inventor
Chappaqua, NY, US
Overview
Patents· 62 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H05KPrinted circuits21%
Y10TTechnical subjects covered by former us classification10%
B23KSoldering or unsoldering8%
C25DProcesses for the electrolytic or electrophoretic production of coatings4%
H01RElectrically-conductive connections3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
C23CCoating metallic material2%
H01BCables2%
PatentTitleYear
10,130,460Stent having exterior path20189,872,394'Substrate via filling'20189,867,704'Cardiac valve fixing device'20189,565,759'Axiocentric scrubbing land grid array contacts and methods for fabrication'20179,433,101'Substrate via filling'20169,379,007'Electromigration-resistant lead-free solder interconnect structures'20169,082,762'Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip'20159,040,841'Axiocentric scrubbing land grid array contacts and methods for fabrication'20158,691,685'Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present'20148,679,964'Prevention and control of intermetallic alloy inclusions'20148,679,899'Multipath soldered thermal interface between a chip and its heat sink'20148,314,500'Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers'20128,263,879'Axiocentric scrubbing land grid array contacts and methods for fabrication'20128,157,158'Modification of solder alloy compositions to suppress interfacial void formation in solder joints'20128,026,613'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20117,932,169'Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers'20117,923,849'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20117,820,488'Microelectronic devices and methods'20107,815,968'Centrifugal method for filing high aspect ratio blind mirco vias powdered materials for circuit formation'20107,784,669'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,703,661'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,523,852'Solder interconnect structure and method using injection molded solder'20097,467,742'Electrically conducting adhesives for via fill applications'20087,452,568'Centrifugal method for filing high aspect ratio blind micro vias with powdered materials for circuit formation'20087,410,833'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20087,329,948'Microelectronic devices and methods'20087,273,803'Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure'20077,115,996'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20067,079,393'Fluidic cooling systems and methods for electronic components'20066,879,098'Display fabrication using modular active devices'20056,805,974'Lead-free tin-silver-copper alloy solder composition'20046,784,088'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20046,698,077'Display fabrication using modular active devices'20046,646,355'Structure comprising beam leads bonded with electrically conductive adhesive'20036,632,314'Method of making a lamination and surface planarization for multilayer thin film interconnect'20036,600,224'Thin film attachment to laminate using a dendritic interconnection'20036,555,762'Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition'20036,551,931'Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped'20036,337,522'Structure employing electrically conductive adhesives'20026,322,685'Apparatus and method for plating coatings on to fine powder materials and use of the powder therefrom'20016,300,164'Structure, materials, and methods for socketable ball grid'20016,297,559'Structure, materials, and applications of ball grid array interconnections'20016,258,703'Reflow of low melt solder tip C4\'s'20016,238,599'High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications'20016,224,690'Flip-Chip interconnections using lead-free solders'20016,120,885'Structure, materials, and methods for socketable ball grid'20006,114,413'Thermally conducting materials and applications for microelectronic packaging'20006,059,952'Method of fabricating coated powder materials and their use for high conductivity paste applications'20005,958,590'Dendritic powder materials for high conductivity paste applications'19995,937,320'Barrier layers for electroplated SnPb eutectic solder joints'19995,855,993'Electronic devices having metallurgies containing copper-semiconductor compounds'19995,837,119'Methods of fabricating dendritic powder materials for high conductivity paste applications'19985,633,047'Electronic devices having metallurgies containing copper-semiconductor compounds'19975,296,189'Method for producing metal powder with a uniform distribution of dispersants, method of uses thereof and structures fabricated therewith'19945,242,569'Thermocompression bonding in integrated circuit packaging'19935,185,073'Method of fabricating nendritic materials'19935,148,261'Thermocompression bonding in integrated circuit packaging'19925,137,461'Separable electrical connection technology'19925,135,155'Thermocompression bonding in integrated circuit packaging'19925,134,460'Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding'19925,120,418'Lead frame plating apparatus for thermocompression bonding'19925,006,917'Thermocompression bonding in integrated circuit packaging'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2018Patents assigned to IBM (57)· patent assignee history
1991–2018Based in Chappaqua, NY, US· patent location history
2012–2015Patents assigned to SHIH DA-YUAN (5)· patent assignee history
2012–2015Patents assigned to KANG SUNG K (4)· patent assignee history
2012–2014Patents assigned to KANG SUNG KWON (3)· patent assignee history
2012–2017Based in Yorktown Heights, NY, US· patent location history
2015Based in Armonk, NY, US· patent location history
2016–2017Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
2018Based in Yongin-si, KR· patent location history
2018Based in Gyeonggi-do, KR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 57 | 1991–2018 |
| SHIH DA-YUAN | 5 | 2012–2015 |
| KANG SUNG Kself | 4 | 2012–2015 |
| KANG SUNG KWONself | 3 | 2012–2014 |
| GLOBALFOUNDRIES INC | 2 | 2016–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chappaqua, New York, US | 54 | 1991–2018 |
| Yorktown Heights, New York, US | 3 | 2012–2017 |
| Yongin-si, KR | 1 | 2018 |
| Gyeonggi-do, KR | 1 | 2018 |
| Armonk, New York, US | 1 | 2015 |