Inventor
Susan Clay Vitkavage
Inventor
Orlando, FL, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10DInorganic electric semiconductor devices18%
Y10TTechnical subjects covered by former us classification10%
H01FMagnets8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B24BMachines, devices, or processes for grinding or polishing3%
C23CCoating metallic material3%
G01NInvestigating or analysing materials by determining their chemical or physical properties3%
PatentTitleYear
7,678,639'Inductor formed in an integrated circuit'20107,541,238'Inductor formed in an integrated circuit'20097,068,139'Inductor formed in an integrated circuit'20066,879,046'Split barrier layer including nitrogen-containing portion and oxygen-containing portion'20056,798,043'Structure and method for isolating porous low-k dielectric films'20046,657,302'Integration of low dielectric material in semiconductor circuit structures'20036,576,980'Surface treatment anneal of hydrogenated silicon-oxy-carbide dielectric layer'20036,548,892'Low k dielectric insulator and method of forming semiconductor circuit structures'20036,432,814'Method of manufacturing an interconnect structure having a passivation layer for preventing subsequent processing reactions'20026,258,231'Chemical mechanical polishing endpoint apparatus using component activity in effluent slurry'20016,214,732'Chemical mechanical polishing endpoint detection by monitoring component activity in effluent slurry'20016,083,810'Integrated circuit fabrication process'20006,028,359'Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor'20005,858,873'Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof'19995,607,543'Integrated circuit etching'19975,244,821'Bipolar fabrication method'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993Patents assigned to AT & T BELL LAB (1)· patent assignee history
1993Based in Zionsville, PA, US· patent location history
1997–2001Patents assigned to LUCENT TECHNOLOGIES INC (5)· patent assignee history
1997–2010Based in Orlando, FL, US· patent location history
2001–2002Patents assigned to AGERE SYST GUARDIAN CORP (2)· patent assignee history
2003–2010Patents assigned to AGERE SYSTEMS INC (8)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| AGERE SYSTEMS INC | 8 | 2003–2010 |
| LUCENT TECHNOLOGIES INC | 5 | 1997–2001 |
| AGERE SYST GUARDIAN CORP | 2 | 2001–2002 |
| AT & T BELL LAB | 1 | 1993 |
Locations
| Location | Patents | Span |
|---|---|---|
| Orlando, Florida, US | 15 | 1997–2010 |
| Zionsville, Pennsylvania, US | 1 | 1993 |