Inventor

Kuo-Tung Chang

Inventor

Saratoga, CA, US

Overview

1994–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 127 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices33%

H10DInorganic electric semiconductor devices29%

G11CStatic stores13%

H01LSemiconductor devices10%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

A47LDomestic washing or cleaning0%

B08BCleaning in general0%

PatentTitleYear

10,872,898Embedded non-volatile memory device and fabrication method of the same2020 10,818,761Memory first process flow and device2020 10,685,724Suppression of program disturb with bit line and select gate voltage regulation2020 10,644,016Charge-trapping memory device2020 10,622,370System and method for manufacturing self-aligned STI with single poly2020 10,516,044Contacts for semiconductor devices2019 10,497,710Split-gate flash cell formed on recessed substrate2019 10,446,245Non-volatile memory array with memory gate line and source line scrambling2019 10,403,731Memory first process flow and device2019 10,242,996Method of forming high-voltage transistor with thin gate poly2019 10,236,299Three-dimensional charge trapping NAND cell with discrete charge trapping film2019 10,229,745Suppression of program disturb with bit line and select gate voltage regulation2019 10,192,627Non-volatile memory array with memory gate line and source line scrambling2019 10,141,393Three dimensional capacitor2018 10,014,380Memory first process flow and device2018 9,997,253Non-volatile memory array with memory gate line and source line scrambling2018 9,966,477Charge trapping split gate device and method of fabricating same2018 9,922,833'Charge trapping split gate embedded flash memory and associated methods'2018 9,917,166'Memory first process flow and device'2018 9,881,683'Suppression of program disturb with bit line and select gate voltage regulation'2018 9,853,039Split-gate flash cell formed on recessed substrate2017 9,818,755'Split-gate flash cell formed on recessed substrate'2017 9,616,467'Cleaning apparatus'2017 9,508,736'Three-dimensional charge trapping NAND cell with discrete charge trapping film'2016 9,368,588'Integrated circuits with non-volatile memory and methods for manufacture'2016 9,368,606'Memory first process flow and device'2016 9,276,007'System and method for manufacturing self-aligned STI with single poly'2016 9,245,895'Oro and orpro with bit line trench to suppress transport program disturb'2016 9,190,531'Flash memory cell with flair gate'2015 9,153,596'Adjacent wordline disturb reduction using boron/indium implant'2015 8,836,006'Integrated circuits with non-volatile memory and methods for manufacture'2014 8,816,438'Process charging protection for split gate charge trapping flash'2014 8,815,727'Integrated circuit with metal and semi-conducting gate'2014 8,802,537'System and method for improving reliability in a semiconductor device'2014 8,785,268'Memory system with Fin FET technology'2014 8,658,496'Etch stop layer for memory cell reliability improvement'2014 8,647,969'Method for forming a semiconductor layer with improved gap filling properties'2014 8,642,441'Self-aligned STI with single poly for manufacturing a flash memory device'2014 8,598,645'System and method for improving mesa width in a semiconductor device'2013 8,587,049'Memory cell system with charge trap'2013 8,564,041'Contacts for semiconductor devices'2013 8,455,268'Gate replacement with top oxide regrowth for the top oxide improvement'2013 8,367,537'Flash memory cell with a flair gate'2013 8,329,598'Sacrificial nitride and gate replacement'2012 8,319,266'Etch stop layer for memory cell reliability improvement'2012 8,283,718'Integrated circuit system with metal and semi-conducting gate'2012 8,208,296'Apparatus and method for extended nitride layer in a flash memory'2012 8,183,623'Dual charge storage node memory device and methods for fabricating such device'2012 8,144,522'Erasing flash memory using adaptive drain and/or gate bias'2012 8,143,661'Memory cell system with charge trap'2012 8,133,801'Method for forming a semiconducting layer with improved gap filling properties'2012 8,114,736'Integrated circuit system with memory system'2012 8,076,712'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'2011 8,012,830'ORO and ORPRO with bit line trench to suppress transport program disturb'2011 7,998,846'3-D integrated circuit system and method'2011 7,995,386'Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb'2011 7,981,745'Sacrificial nitride and gate replacement'2011 7,952,938'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory'2011 7,943,980'Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications'2011 7,915,123'Dual charge storage node memory device and methods for fabricating such device'2011 7,906,395'Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications'2011 7,906,807'Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics'2011 7,907,448'Scaled down select gates of NAND flash memory cell strings and method of forming same'2011 7,851,306'Method for forming a flash memory device with straight word lines'2010 7,842,618'System and method for improving mesa width in a semiconductor device'2010 7,803,680'Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications'2010 7,778,088'Erasing flash memory using adaptive drain and/or gate bias'2010 7,776,688'Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics'2010 7,767,517'Semiconductor memory comprising dual charge storage nodes and methods for its fabrication'2010 7,746,705'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory'2010 7,746,698'Programming in memory devices using source bitline voltage bias'2010 7,696,038'Methods for fabricating flash memory devices'2010 7,679,129'System and method for improving oxide-nitride-oxide (ONO) coupling in a semiconductor device'2010 7,675,104'Integrated circuit memory system employing silicon rich layers'2010 7,666,739'Methods for fabricating a split charge storage node semiconductor memory'2010 7,659,569'Work function engineering for FN erase of a memory device with multiple charge storage elements in an undercut region'2010 7,632,749'Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer'2009 7,622,389'Selective contact formation using masking and resist patterning techniques'2009 7,599,228'Flash memory device having increased over-erase correction efficiency and robustness against device variations'2009 7,564,091'Memory device and methods for its fabrication'2009 7,488,657'Method and system for forming straight word lines in a flash memory array'2009 7,489,560'Reduction of leakage current and program disturbs in flash memory devices'2009 7,439,141'Shallow trench isolation approach for improved STI corner rounding'2008 7,432,156'Memory device and methods for its fabrication'2008 7,382,650'Method and apparatus for sector erase operation in a flash memory array'2008 7,323,726'Method and apparatus for coupling to a common line in an array'2008 7,301,193'Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell'2007 7,217,964'Method and apparatus for coupling to a source line in a memory device'2007 7,170,130'Memory cell with reduced DIBL and Vss resistance'2007 7,151,028'Memory cell with plasma-grown oxide spacer for reduced DIBL and Vss resistance and increased reliability'2006 7,151,027'Method and device for reducing interface area of a memory device'2006 7,029,975'Method and apparatus for eliminating word line bending by source side implantation'2006 7,019,366'Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance'2006 6,992,370'Memory cell structure having nitride layer with reduced charge loss and method for fabricating same'2006 6,927,129'Narrow wide spacer'2005 6,919,247'Method of fabricating a floating gate'2005 6,803,272'Use of high-K dielectric material in modified ONO structure for semiconductor devices'2004 6,753,570'Memory device and method of making'2004 6,674,138'Use of high-k dielectric materials in modified ONO structure for semiconductor devices'2004 6,613,657'BPSG, SA-CVD liner/P-HDP gap fill'2003 6,576,487'Method to distinguish an STI outer edge current component with an STI normal current component'2003 6,548,855'Non-volatile memory dielectric as charge pump dielectric'2003 6,545,310'Non-volatile memory with a serial transistor structure with isolated well and method of operation'2003 6,438,030'Non-volatile memory, method of manufacture, and method of programming'2002 6,433,382'Split-gate vertically oriented EEPROM device and process'2002 6,295,229'Semiconductor device and method of operating it'2001 6,246,088'Nonvolatile memory circuit and structure'2001 5,981,340'Method of building an EPROM cell without drain disturb and reduced select gate resistance'1999 5,969,383'Split-gate memory device and method for accessing the same'1999 5,824,584'Method of making and accessing split gate memory device'1998 5,740,109'Non-linear charge pump'1998 5,706,228'Method for operating a memory array'1998 5,646,060'Method for making an EEPROM cell with isolation transistor'1997 5,585,293'Fabrication process for a 1-transistor EEPROM memory device capable of low-voltage operation'1996 5,554,869'Electrically programmable read-only memory array'1996 5,498,559'Method of making a nonvolatile memory device with five transistors'1996 5,494,838'Process of making EEPROM memory device having a sidewall spacer floating gate electrode'1996 5,471,422'EEPROM cell with isolation transistor and methods for making and operating the same'1995 5,467,308'Cross-point eeprom memory array'1995 5,429,969'Process for forming electrically programmable read-only memory cell with a merged select/control gate'1995 5,422,504'EEPROM memory device having a sidewall spacer floating gate electrode and process'1995 5,422,846'Nonvolatile memory having overerase protection'1995 5,414,693'Self-aligned dual-bit split gate (DSG) flash EEPROM cell'1995 5,408,115'Self-aligned, split-gate EEPROM device'1995 5,364,806'Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell'1994 5,280,446'Flash eprom memory circuit having source side programming'1994 5,278,439'Self-aligned dual-bit split gate (DSG) flash EEPROM cell'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2003Based in San Jose, CA, US· patent location history

1995–2003Patents assigned to MOTOROLA INC (21)· patent assignee history

1995–2002Based in Austin, TX, US· patent location history

2003–2014Patents assigned to ADVANCED MICRO DEVICES INC (18)· patent assignee history

2003–2020Based in Saratoga, CA, US· patent location history

2006–2016Patents assigned to SPANSION LLC (63)· patent assignee history

2011–2016Patents assigned to CHANG KUO-TUNG (19)· patent assignee history

2015–2020Patents assigned to CYPRESS SEMICONDUCTOR CORP (27)· patent assignee history

2017Based in Beijing, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SPANSION LLC	63	2006–2016
CYPRESS SEMICONDUCTOR CORP	27	2015–2020
MOTOROLA INC	21	1995–2003
CHANG KUO-TUNGself	19	2011–2016
ADVANCED MICRO DEVICES INC	18	2003–2014

Locations

Location	Patents	Span
Saratoga, California, US	101	2003–2020
Austin, Texas, US	20	1995–2002
San Jose, California, US	5	1994–2003
Beijing, CN	1	2017