Inventor
Pranav Kalavade
Inventor
San Jose, CA, US
Overview
Patents· 78 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores54%
G06FElectric digital data processing29%
H10DInorganic electric semiconductor devices5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
H03MCoding3%
H10BElectronic memory devices3%
G11BInformation storage based on relative movement between record carrier and transducer1%
PatentTitleYear
11,056,203Boosted bitlines for storage cell programmed state verification in a memory array202111,029,861Sense flags in a memory device202110,942,799Defective bit line management in connection with a memory access202110,871,903Achieving consistent read times in multi-level non-volatile memory202010,839,916One-sided soft reads202010,832,766Program verification time reduction in non-volatile memory devices202010,777,277Configuration of a memory device for programming memory cells202010,699,790Erase and soft program for vertical NAND flash202010,658,053Ramping inhibit voltage during memory programming202010,629,271Method and system for reducing program disturb degradation in flash memory202010,599,515Transfer of encoded data stored in non-volatile memory for decoding by a controller of a memory device202010,482,974Operation of a memory device during programming201910,453,535Segmented erase in memory201910,454,495Apparatus and method for mapping binary to ternary and its reverse201910,438,656System and method for performing a concurrent multiple page read of a memory array201910,430,114Buffer operations in memory201910,409,506Sense flags in a memory device201910,379,738Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation201910,303,571Data recovery in memory devices201910,290,356Erase and soft program for vertical NAND flash201910,289,313Method and apparatus for improving sequential reading in NAND flash201910,276,252Data storage device with operation based on temperature difference201910,275,156Managing solid state drive defect redundancies at sub-block granularity201910,254,977Achieving consistent read times in multi-level non-volatile memory201910,242,734Resuming storage die programming after power loss201910,217,515Programming memory devices201910,141,071Predictive count fail byte (CFBYTE) for non-volatile memory201810,126,967Sense operation flags in a memory device201810,120,751Techniques to recover data using exclusive OR (XOR) parity information201810,109,361Coarse pass and fine pass multi-level NVM programming201810,102,903Write process for a non volatile memory device201810,043,574Programming memories with multi-level pass signal20189,977,622Buffer operations in memory20189,922,704'Programming memories with multi-level pass signal'20189,910,594'Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation'20189,870,169'Interleaved all-level programming of non-volatile memory'20189,865,357'Performing read operations on a memory device'20189,852,065Method and apparatus for reducing data program completion overhead in NAND flash20179,851,905Concurrent memory operations for read operation preemption20179,819,362'Apparatus and method for detecting and mitigating bit-line opens in flash memory'20179,811,269'Achieving consistent read times in multi-level non-volatile memory'20179,792,997'Ramping inhibit voltage during memory programming'20179,754,683'Method and system to obtain state confidence data using multistrobe read of a non-volatile memory'20179,740,419'Methods and apparatus to preserve data of a solid state drive during a power loss event'20179,703,494'Method and apparatus for protecting lower page data during programming in NAND flash'20179,672,102'NAND memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages'20179,576,674'Memory cell sensing'20179,570,159'Methods and apparatus to preserve data of a solid state drive during a power loss event'20179,535,777'Defect management policies for NAND flash memory'20179,519,582'Sense operation flags in a memory device'20169,484,101'Methods of programming memories'20169,418,752'Ramping inhibit voltage during memory programming'20169,418,000'Dynamically compensating for degradation of a non-volatile memory device'20169,396,791'Programming memories with multi-level pass signal'20169,330,777'Memory program disturb reduction'20169,305,654'Erase and soft program for vertical NAND flash'20169,245,645'Multi-pulse programming for memory'20169,230,666'Drain select gate voltage management'20169,135,998'Sense operation flags in a memory device'20159,105,337'Memories and methods of programming memories'20159,099,183'Program VT spread folding for NAND flash memory programming'20159,043,681'Reconstructing codewords using a side channel'20159,001,577'Memory cell sensing'20158,982,625'Memory program disturb reduction'20158,943,385'NAND memory management'20158,767,487'Drain select gate voltage management'20148,681,562'Memories and methods of programming memories'20148,638,612'Automatic selective slow program convergence'20148,542,531'Charge equilibrium acceleration in a floating gate memory device via a reverse field pulse'20138,411,508'Automatic selective slow program convergence'20138,400,831'Method and apparatus for improving endurance of flash memories'20138,248,862'Source bias shift for multilevel memories'20128,072,022'Apparatus and methods for improved flash cell characteristics'20117,663,172'Vertical memory device and method'20107,615,428'Vertical memory device and method'20097,312,490'Vertical memory device and method'20076,821,851'Method of making ultra thin body vertical replacement gate MOSFET'20046,635,924'Ultra thin body vertical replacement gate MOSFET'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2021Based in San Jose, CA, US· patent location history
2007–2021Patents assigned to INTEL CORP (50)· patent assignee history
2011–2019Patents assigned to KALAVADE PRANAV (15)· patent assignee history
2013–2021Patents assigned to MICRON TECHNOLOGY INC (25)· patent assignee history
2013–2017Patents assigned to PARAT KRISHNA K (4)· patent assignee history
2014–2019Patents assigned to GODA AKIRA (4)· patent assignee history
2018–2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 50 | 2007–2021 |
| MICRON TECHNOLOGY INC | 25 | 2013–2021 |
| KALAVADE PRANAVself | 15 | 2011–2019 |
| GODA AKIRA | 4 | 2014–2019 |
| PARAT KRISHNA K | 4 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 76 | 2003–2021 |
| Santa Clara, California, US | 2 | 2018–2019 |