Inventor

Sylvain Joblot

Inventor
Bizonnes, FR

Overview

20→
Patents
2010–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10DInorganic electric semiconductor devices11%
H01PWaveguides9%
Y10TTechnical subjects covered by former us classification9%
H03HImpedance networks, e.g. resonant circuits8%
H01GCapacitors6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G02BOptical elements, systems or apparatus5%
C30BSingle-crystal growth2%
PatentTitleYear
9,818,646'Process for fabricating an integrated circuit comprising at least one coplanar waveguide'20179,728,337'Method for producing a capacitor'20179,673,088'Process for fabricating an integrated circuit comprising at least one coplanar waveguide'20179,647,625'Method for manufacturing BAW resonators on a semiconductor wafer'20179,455,191'Shielded coplanar line'20169,324,612'Shielded coplanar line'20169,240,624'Process for fabricating an integrated circuit comprising at least one coplanar waveguide'20169,224,796'Process for producing a through-silicon via and a through-silicon capacitor in a substrate, and corresponding device'20159,147,725'Semiconductor device comprising an integrated capacitor and method of fabrication'20158,994,172'Connection of a chip provided with through vias'20158,988,893'Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device'20158,975,737'Transmission line for electronic circuits'20158,841,748'Semiconductor device comprising a capacitor and an electrical connection via and fabrication method'20148,841,749'Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method'20148,756,778'Method of adjustment during manufacture of a circuit having a capacitor'20148,704,358'Method for forming an integrated circuit'20148,593,234'Bragg mirror and BAW resonator with a high quality factor on the bragg mirror'20138,587,921'Method of adjustment on manufacturing of a circuit having a resonant element'20138,397,360'Method for manufacturing a monolithic oscillator with bulk acoustic wave (BAW) resonators'20137,785,991'Process for integrating a III-N type component on a (001) nominal silicium substrate'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2017Patents assigned to ST MICROELECTRONICS SA (19)· patent assignee history
2010Based in Sassenage, FR· patent location history
2013–2016Patents assigned to BAR PIERRE (9)· patent assignee history
2013–2016Patents assigned to JOBLOT SYLVAIN (9)· patent assignee history
2013–2015Patents assigned to CARPENTIER JEAN-FRANCOIS (5)· patent assignee history
2013–2014Patents assigned to PETIT DAVID (3)· patent assignee history
2013–2014Based in Valbonne, FR· patent location history
2014–2017Based in Bizonnes, FR· patent location history
2014Based in La Tronche, FR· patent location history
2015Based in Grenoble, FR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ST MICROELECTRONICS SA192010–2017
BAR PIERRE92013–2016
JOBLOT SYLVAINself92013–2016
CARPENTIER JEAN-FRANCOIS52013–2015
PETIT DAVID32013–2014
Locations
LocationPatentsSpan
Bizonnes, FR122014–2017
Valbonne, FR42013–2014
La Tronche, FR22014
Grenoble, FR12015
Sassenage, FR12010