LexDanaLexDanabeta
Inventor

Bruce James Mathewson

Inventor
Papworth Everard, GB

Overview

43→
Patents
1998–2021
Patent span
Physics
Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing73%
H04LTransmission of digital information, e.g. telegraphic communication15%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
G11CStatic stores2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
11,055,250Non-forwardable transfers202110,970,225Apparatus and method for handling cache maintenance operations202110,963,409Interconnect circuitry and a method of operating such interconnect circuitry202110,949,292Memory interface having data signal path and tag signal path202110,917,198Transfer protocol in a data processing network202110,817,336Apparatus and method to schedule time-sensitive tasks202010,795,820Read transaction tracker lifetimes in a coherent interconnect system202010,783,080Cache maintenance operations in a data processing system202010,732,854Runtime configuration of a data processing system202010,664,399Filtering coherency protocol transactions202010,613,996Separating completion and data responses for higher read throughput and lower link utilization in a data processing network202010,579,526Responding to snoop requests202010,489,323Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave201910,324,858Access control201910,282,297Read-with overridable-invalidate transaction201910,223,002Compare-and-swap transaction201910,185,663Cache bypass20199,830,294Data processing system and method for handling multiple transactions using a multi-transaction request20179,569,365'Store-exclusive instruction conflict resolution'20179,477,623'Barrier transactions in interconnects'20168,856,408'Reduced latency barrier transaction requests in interconnects'20148,732,400'Data store maintenance requests in interconnects'20148,607,006'Barrier transactions in interconnects'20138,589,631'Coherency control with writeback ordering'20138,463,966'Synchronising activities of various components in a distributed system'20138,463,958'Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices'20138,375,170'Apparatus and method for handling data in a cache'20138,190,801'Interconnect logic for a data processing apparatus'20128,045,573'Bit ordering for packetised serial data transmission on an integrated circuit'20117,925,840'Data processing apparatus and method for managing snoop operations'20117,757,027'Control of master/slave communication within an integrated circuit'20107,599,998'Message handling communication between a source processor core and destination processor cores'20097,353,297'Handling of write transactions in a data processing apparatus'20087,290,075'Performing arbitration in a data processing apparatus'20077,254,658'Write transaction interleaving'20077,219,178'Bus deadlock avoidance'20077,213,092'Write response signalling within a communication bus'20077,213,095'Bus transaction management within data processing systems'20077,143,221'Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus'20067,117,277'Flexibility of design of a bus interconnect block for a data processing apparatus'20067,069,376'Flexibility of use of a data processing apparatus'20066,959,351'Handling of a multi-access instruction in a data processing apparatus'20055,809,037'Integrated circuit testing'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2021Patents assigned to ADVANCED RISC MACH LTD (43)· patent assignee history
1998Based in Milton Keynes, GB· patent location history
2005–2021Based in Papworth Everard, GB· patent location history
2006–2021Based in Cambridge, GB· patent location history
2007Based in Cambs, GB· patent location history
2012–2017Patents assigned to MATHEWSON BRUCE JAMES (9)· patent assignee history
2012Based in Cambridgeshire, GB· patent location history
2013–2017Patents assigned to GRISENTHWAITE RICHARD ROY (6)· patent assignee history
2013–2014Patents assigned to LAYCOCK CHRISTOPHER WILLIAM (6)· patent assignee history
2013–2014Patents assigned to RIOCREUX PETER ANDREW (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED RISC MACH LTD431998–2021
MATHEWSON BRUCE JAMESself92012–2017
GRISENTHWAITE RICHARD ROY62013–2017
LAYCOCK CHRISTOPHER WILLIAM62013–2014
RIOCREUX PETER ANDREW42013–2014
Locations
LocationPatentsSpan
Papworth Everard, GB312005–2021
Cambridge, GB92006–2021
Cambridgeshire, GB12012
Cambs, GB12007
Milton Keynes, GB11998