Inventor
James Kai
Inventor
Santa Clara, CA, US
Overview
Patents· 136 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices28%
H10DInorganic electric semiconductor devices19%
H01LSemiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
G11CStatic stores5%
H10NElectric solid-state devices not otherwise provided for2%
B82YSpecific uses or applications of nanostructures2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
B28DWorking stone or stone-like materials1%
PatentTitleYear
11,127,729Method for removing a bulk substrate from a bonded assembly of wafers202111,043,455Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same202111,037,943Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same202111,018,153Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes202110,985,169Three-dimensional device with bonded structures including a support die and methods of making the same202110,950,626Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes202110,943,917Three-dimensional memory device with drain-select-level isolation structures and method of making the same202110,840,260Through-array conductive via structures for a three-dimensional memory device and methods of making the same202010,825,827Non-volatile memory with pool capacitor202010,818,685Non-volatile memory with pool capacitor202010,748,927Three-dimensional memory device with drain-select-level isolation structures and method of making the same202010,748,894Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same202010,727,216Method for removing a bulk substrate from a bonded assembly of wafers202010,685,978Three-dimensional memory device with drain-select-level isolation structures and method of making the same202010,685,979Three-dimensional memory device with drain-select-level isolation structures and method of making the same202010,629,616Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer202010,622,368Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof202010,622,369Three-dimensional memory device including contact via structures that extend through word lines and method of making the same202010,559,588Three-dimensional flat inverse NAND memory device and method of making the same202010,490,569Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings201910,490,568Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof201910,431,313Grouping memory cells into sub-blocks for program speed uniformity201910,403,639Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same201910,388,666Concurrent formation of memory openings and contact openings for a three-dimensional memory device201910,381,443Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device201910,355,015Three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block201910,355,009Concurrent formation of memory openings and contact openings for a three-dimensional memory device201910,297,610Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same201910,290,643Three-dimensional memory device containing floating gate select transistor201910,269,817Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof201910,262,945Three-dimensional array device having a metal containing barrier and method of making thereof201910,224,407High voltage field effect transistor with laterally extended gate dielectric and method of making thereof201910,121,794Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof201810,050,054Three-dimensional memory device having drain select level isolation structure and method of making thereof201810,038,006Through-memory-level via structures for a three-dimensional memory device201810,020,363Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device201810,008,570Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device20189,985,098Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device20189,972,640Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof20189,959,932Grouping memory cells into sub-blocks for program speed uniformity20189,953,992Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof20189,935,123Within array replacement openings for a three-dimensional memory device20189,922,987'Three-dimensional memory device containing separately formed drain select transistors and method of making thereof'20189,917,100'Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same'20189,831,266Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same20179,824,966'Three-dimensional memory device containing a lateral source contact and method of making the same'20179,818,693'Through-memory-level via structures for a three-dimensional memory device'20179,818,759'Through-memory-level via structures for a three-dimensional memory device'20179,805,805'Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof'20179,728,546'3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same'20179,698,149'Non-volatile memory with flat cell structures and air gap isolation'20179,620,514'3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same'20179,576,975'Monolithic three-dimensional NAND strings and methods of fabrication thereof'20179,552,991'Trench vertical NAND and method of making thereof'20179,548,311'Non-volatile storage element with suspended charge storage region'20179,524,779'Three dimensional vertical NAND device with floating gates'20169,502,471'Multi tier three-dimensional memory devices including vertically shared bit lines'20169,466,644'Resistance-switching memory cell with multiple raised structures in a bottom electrode'20169,449,982'Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks'20169,437,813'Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask'20169,379,120'Metal control gate structures and air gap isolation in non-volatile memory'20169,349,740'Non-volatile storage element with suspended charge storage region'20169,331,181'Nanodot enhanced hybrid floating gate for non-volatile memory devices'20169,252,151'Three dimensional NAND device with birds beak containing floating gates and method of making thereof'20169,230,971'NAND string containing self-aligned control gate sidewall cladding'20169,224,746'Inverted-T word line and formation for non-volatile storage'20159,177,808'Memory device with control gate oxygen diffusion control and method of making thereof'20159,165,940'Three dimensional NAND device with silicide containing floating gates and method of making thereof'20159,123,890'Resistance-switching memory cell with multiple raised structures in a bottom electrode'20159,099,496'Method of forming an active area with floating gate negative offset profile in FG NAND memory'20159,030,016'Semiconductor device with copper interconnects separated by air gaps'20159,029,936'Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof'20158,987,802'Method for using nanoparticles to make uniform discrete floating gate layer'20158,987,087'Three dimensional NAND device with birds beak containing floating gates and method of making thereof'20158,969,153'NAND string containing self-aligned control gate sidewall cladding'20158,946,048'Method of fabricating non-volatile memory with flat cell structures and air gap isolation'20158,946,803'Method of forming a floating gate with a wide base and a narrow stem'20158,946,022'Integrated nanostructure-based non-volatile memory fabrication'20158,928,061'Three dimensional NAND device with silicide containing floating gates'20158,877,586'Process for forming resistive switching memory cells using nano-particles'20148,823,075'Select gate formation for nanodot flat cell'20148,822,288'NAND memory device containing nanodots and method of making thereof'20148,737,111'Memory cell with resistance-switching layers'20148,710,481'Non-volatile memory cell containing a nano-rail electrode'20148,575,000'Copper interconnects separated by air gaps and method of making thereof'20138,546,152'Enhanced endpoint detection in non-volatile memory fabrication processes'20138,520,424'Composition of memory cell with resistance-switching layers'20138,492,224'Metal control gate structures and air gap isolation in non-volatile memory'20138,461,641'Ultrahigh density vertical NAND memory device and method of making thereof'20138,455,939'Stacked metal fin cell'20138,383,479'Integrated nanostructure-based non-volatile memory fabrication'20138,330,208'Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof'20128,263,465'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer'20128,222,091'Damascene method of making a nonvolatile memory device'20128,207,036'Method for forming self-aligned dielectric cap above floating gate'20128,193,055'Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution'20128,187,936'Ultrahigh density vertical NAND memory device and method of making thereof'20128,143,156'Methods of forming high density semiconductor devices using recursive spacer technique'20128,105,867'Self-aligned three-dimensional non-volatile memory fabrication'20128,097,498'Damascene method of making a nonvolatile memory device'20128,030,160'Methods of forming NAND flash memory with fixed charge'20117,960,266'Spacer patterns using assist layer for high density semiconductor devices'20117,939,407'Composite charge storage structure formation in non-volatile memory using etch stop technologies'20117,919,809'Dielectric layer above floating gate for reducing leakage current'20117,915,124'Method of forming dielectric layer above floating gate for reducing leakage current'20117,915,664'Non-volatile memory with sidewall channels and raised source/drain regions'20117,888,210'Non-volatile memory fabrication and isolation for composite charge storage structures'20117,807,529'Lithographically space-defined charge storage regions in non-volatile memory'20107,795,080'Methods of forming integrated circuit devices using composite spacer structures'20107,773,403'Spacer patterns using assist layer for high density semiconductor devices'20107,736,973'Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming'20107,732,275'Methods of forming NAND flash memory with fixed charge'20107,723,186'Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer'20107,704,832'Integrated non-volatile memory and peripheral circuitry fabrication'20107,619,926'NAND flash memory with fixed charge'20097,615,447'Composite charge storage structure formation in non-volatile memory using etch stop technologies'20097,592,225'Methods of forming spacer patterns using assist layer for high density semiconductor devices'20097,592,223'Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation'20097,582,529'Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation'20097,495,282'NAND memory with virtual channel'20097,494,870'Methods of forming NAND memory with virtual channel'20097,279,410'Method for forming inlaid structures for IC interconnections'20076,767,827'Method for forming dual inlaid structures for IC interconnections'20046,670,265'Low K dielectic etch in high density plasma etcher'20036,632,707'Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning'20036,554,046'Substrate cleaving tool and method'20036,513,564'Nozzle for cleaving substrates'20036,514,860'Integration of organic fill for dual damascene process'20036,424,039'Dual damascene process using sacrificial spin-on materials'20026,297,167'In-situ etch of multiple layers during formation of local interconnects'20016,263,941'Nozzle for cleaving substrates'20016,221,740'Substrate cleaving tool and method'20016,057,239'Dual damascene process using sacrificial spin-on materials'20005,920,796'In-situ etch of BARC layer during formation of local interconnects'19995,841,196'Fluted via formation for superior metal step coverage'19985,746,884'Fluted via formation for superior metal step coverage'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2003Based in San Francisco, CA, US· patent location history
2003–2021Based in Santa Clara, CA, US· patent location history
2009–2011Patents assigned to SANDISK CORP (20)· patent assignee history
2011–2017Patents assigned to SANDISK TECHNOLOGIES INC (42)· patent assignee history
2012–2015Patents assigned to MATAMIS GEORGE (17)· patent assignee history
2012–2015Patents assigned to KAI JAMES (13)· patent assignee history
2015–2017Based in Fremont, CA, US· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (60)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 60 | 2016–2021 |
| SANDISK TECHNOLOGIES INC | 42 | 2011–2017 |
| SANDISK CORP | 20 | 2009–2011 |
| MATAMIS GEORGE | 17 | 2012–2015 |
| KAI JAMESself | 13 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 122 | 2003–2021 |
| San Francisco, California, US | 12 | 1998–2003 |
| Fremont, California, US | 2 | 2015–2017 |