Inventor

Jae-Seok Yang

Inventor

Hwaseong-si, KR

Overview

20→

Patents

2006–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices19%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

H10DInorganic electric semiconductor devices16%

G06FElectric digital data processing13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%

A01KAnimal husbandry3%

C07KPeptides3%

C12NMicroorganisms or enzymes3%

H03KPulse technique3%

PatentTitleYear

10,872,859Semiconductor device2020 10,699,998Semiconductor devices with insulated source/drain jumper structures2020 10,546,855Integrated circuit (IC) devices including cross gate contacts2020 10,474,783Semiconductor device, method of designing a layout of a semiconductor device, and method of manufacturing a semiconductor device2019 10,361,198Integrated circuit devices and method of manufacturing the same2019 10,249,605Integrated circuit devices2019 10,217,742Semiconductor device having dummy active fin patterns2019 10,216,082Layout design system, system and method for fabricating mask pattern using the same2019 10,177,093Semiconductor devices and methods of manufacturing the same2019 10,147,684Integrated circuit devices2018 9,929,156'Semiconductor device having dummy active fin patterns'2018 9,928,330'Method of decomposing layout of semiconductor device and method of manufacturing semiconductor device using the same'2018 9,874,810Layout decomposition methods and systems2018 9,841,672'Method of decomposing layout of semiconductor device for quadruple patterning technology process and method of manufacturing semiconductor device using the same'2017 9,812,356'Method for manufacturing a semiconductor device'2017 9,652,578'Layout design methods and layout design systems for performing the layout design methods'2017 9,575,112'Test system that performs simultaneous tests of multiple test units'2017 9,357,754'Transgenic pig expressing sTNFR1-Fc genes and the uses thereof'2016 9,018,439'Transgenic pig in which HO-1 and TNFR1-Fc are simultaneously expressed, and method for producing same'2015 7,100,125'Aggressor classification method for analyzing crosstalk of circuit'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2020Patents assigned to SAMSUNG ELECTRONICS CO LTD (18)· patent assignee history

2006Based in Yongin, KR· patent location history

2015–2019Patents assigned to YANG JAE SEOK (4)· patent assignee history

2015–2016Patents assigned to AHN CURIE (2)· patent assignee history

2015–2016Patents assigned to CHO BUM RAE (2)· patent assignee history

2015–2016Patents assigned to HWANG JONG IK (2)· patent assignee history

2015–2016Based in Seoul, KR· patent location history

2017–2020Based in Hwaseong-si, KR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SAMSUNG ELECTRONICS CO LTD	18	2006–2020
YANG JAE SEOKself	4	2015–2019
AHN CURIE	2	2015–2016
CHO BUM RAE	2	2015–2016
HWANG JONG IK	2	2015–2016

Locations

Location	Patents	Span
Hwaseong-si, KR	17	2017–2020
Seoul, KR	2	2015–2016
Yongin, KR	1	2006