LexDanaLexDanabeta
Inventor

Erdem Kaltalioglu

Inventor
Newburgh, NY, US

Overview

74→
Patents
2001–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 74 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H01LSemiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10DInorganic electric semiconductor devices10%
G01RMeasuring electric variables2%
H01GCapacitors1%
H10BElectronic memory devices1%
Y10TTechnical subjects covered by former us classification1%
B24BMachines, devices, or processes for grinding or polishing1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
10,770,407IC structure with interdigitated conductive elements between metal guard structures202010,438,890Interconnect structure having power rail structure and related method201910,388,617Mechanically anchored C4 pad and method of forming same201910,325,862Wafer rigidity with reinforcement structure201910,304,783Wafer reinforcement to reduce wafer curvature201910,297,546Interconnect structures for a security application20199,997,456Interconnect structure having power rail structure and related method20189,947,602IC structure integrity sensor having interdigitated conductive elements20189,852,999Wafer reinforcement to reduce wafer curvature20179,768,065'Interconnect structures with variable dopant levels'20179,761,539'Wafer rigidity with reinforcement structure'20179,741,657'TSV deep trench capacitor and anti-fuse structure'20179,553,054'Strain detection structures for bonded wafers and chips'20179,536,779'Selective local metal cap layer formation for improved electromigration behavior'20179,524,916'Structures and methods for determining TDDB reliability at reduced spacings using the structures'20169,478,509'Mechanically anchored backside C4 pad'20169,431,293'Selective local metal cap layer formation for improved electromigration behavior'20169,373,596'Passivated copper chip pads'20169,330,974'Through level vias and methods of formation thereof'20169,305,879'E-fuse with hybrid metallization'20169,123,726'Selective local metal cap layer formation for improved electromigration behavior'20159,082,781'Semiconductor article having a zig-zag guard ring and method of forming the same'20159,059,333'Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding'20159,059,173'Electronic fuse line with modified cap'20159,059,170'Electronic fuse having a damaged region'20159,059,166'Interconnect with hybrid metallization'20159,054,108'Random local metal cap layer formation for improved integrated circuit reliability'20158,906,799'Random local metal cap layer formation for improved integrated circuit reliability'20148,889,491'Method of forming electronic fuse line with modified cap'20148,890,560'Crack sensors for semiconductor devices'20148,860,225'Devices formed with dual damascene process'20148,822,324'Passivated copper chip pads'20148,748,295'Pads with different width in a scribe line region and method for manufacturing these pads'20148,610,238'Crack stop trenches'20138,569,820'Capacitor having a plurality of parallel conductive members'20138,378,439'Methods of manufacturing semiconductor devices and structures thereof'20138,309,435'Crack stops for semiconductor devices'20128,159,254'Crack sensors for semiconductor devices'20128,138,539'Semiconductor devices and methods of manufacture thereof'20128,093,150'Methods of manufacturing semiconductor devices and structures thereof'20128,062,971'Dual damascene process'20118,008,750'Crack stops for semiconductor devices'20117,871,902'Crack stop trenches'20117,858,448'Method of forming support structures for semiconductor devices'20107,843,035'MIM capacitors with catalytic activation layer'20107,795,615'Capacitor integrated in a structure surrounding a die'20107,786,007'Method and apparatus of stress relief in semiconductor structures'20107,626,268'Support structures for semiconductor devices'20097,615,440'Capacitor and method of manufacturing a capacitor'20097,553,703'Methods of forming an interconnect structure'20097,494,915'Back end interconnect with a shaped interface'20097,436,016'MIM capacitor with a cap layer over the conductive plates'20087,368,804'Method and apparatus of stress relief in semiconductor structures'20087,332,812'Memory card with connecting portions for connection to an adapter'20087,307,346'Final passivation scheme for integrated circuits'20077,268,383'Capacitor and method of manufacturing a capacitor'20077,241,681'Bilayered metal hardmasks for use in dual damascene etch schemes'20077,201,634'Polishing methods and apparatus'20077,125,792'Dual damascene structure and method'20067,122,462'Back end interconnect with a shaped interface'20067,091,612'Dual damascene structure and method'20067,060,619'Reduction of the shear stress in copper via\'s in organic interlayer dielectric material'20067,052,621'Bilayered metal hardmasks for use in Dual Damascene etch schemes'20066,960,835'Stress-relief layer for semiconductor applications'20056,949,442'Methods of forming MIM capacitors'20056,914,320'Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof'20056,887,783'Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof'20056,806,579'Robust via structure and method'20046,806,182'Method for eliminating via resistance shift in organic ILD'20046,730,982'FBEOL process for Cu metallizations free from Al-wirebond pads'20046,638,851'Dual hardmask single damascene integration scheme in an organic low k ILD'20036,613,664'Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices'20036,387,754'Method of forming an on-chip decoupling capacitor with bottom hardmask'20026,278,147'On-chip decoupling capacitor with bottom hardmask'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2019Patents assigned to IBM (26)· patent assignee history
2001–2010Based in Wappingers Falls, NY, US· patent location history
2003–2016Patents assigned to INFINEON TECHNOLOGIES AG (38)· patent assignee history
2004–2010Based in Hsinchu, TW· patent location history
2005–2009Based in Fishkill, NY, US· patent location history
2007–2020Based in Newburgh, NY, US· patent location history
2011–2016Patents assigned to KALTALIOGLU ERDEM (12)· patent assignee history
2011–2014Patents assigned to RIESS PHILIPP (4)· patent assignee history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (12)· patent assignee history
2016Based in Iselin, NJ, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INFINEON TECHNOLOGIES AG382003–2016
IBM262001–2019
GLOBALFOUNDRIES INC122016–2020
KALTALIOGLU ERDEMself122011–2016
RIESS PHILIPP42011–2014
Locations
LocationPatentsSpan
Newburgh, New York, US482007–2020
Hsinchu, TW102004–2010
Wappingers Falls, New York, US102001–2010
Fishkill, New York, US32005–2009
Iselin, New Jersey, US12016