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Inventor

Yasuhiro Kasama

Inventor
Tokyo, JP

Overview

24→
Patents
1990–2009
Patent span
Electricity
Primary field (CPC H)

Patents· 24 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores35%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10BElectronic memory devices21%
H10DInorganic electric semiconductor devices13%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G06FElectric digital data processing1%
PatentTitleYear
7,499,340'Semiconductor memory device and defect remedying method thereof'20097,345,929'Semiconductor memory device and defect remedying method thereof'20087,203,101'Semiconductor memory device and defect remedying method thereof'20077,016,236'Semiconductor memory device and defect remedying method thereof'20066,898,130'Semiconductor memory device and defect remedying method thereof'20056,657,901'Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit'20036,515,913'Semiconductor memory device and defect remedying method thereof'2003RE037539'Sealed stacked arrangement of semiconductor devices'20026,335,884'Semiconductor memory device and defect remedying method thereof'20026,212,089'Semiconductor memory device and defect remedying method thereof'20016,160,744'Semiconductor memory device and defect remedying method thereof'20006,049,500'Semiconductor memory device and defect remedying method thereof'20005,983,358'Semiconductor memory having redundancy circuit'19995,854,508'Semiconductor memory device having zigzag bonding pad arrangement'19985,701,031'Sealed stacked arrangement of semiconductor devices'19975,602,771'Semiconductor memory device and defect remedying method thereof'19975,579,256'Semiconductor memory device and defect remedying method thereof'19965,332,922'Multi-chip semiconductor package'19945,268,868'Output buffer circuits for reducing ground bounce noise'19935,208,782'Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement'19935,043,947'Semiconductor memory device'19915,018,101'Semiconductor memory'19914,956,811'Semiconductor memory'19904,941,129'Semiconductor memory device'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2009Patents assigned to HITACHI LTD (21)· patent assignee history
1990–2009Patents assigned to HITACHI VLSI ENG (9)· patent assignee history
1990–2009Based in Tokyo, JP· patent location history
1999Patents assigned to HITACHI DEVICE ENG (1)· patent assignee history
1999Patents assigned to HITACHI ULSI ENG CORP (1)· patent assignee history
1999Based in Musashino, JP· patent location history
2002Based in Kokubunji, JP· patent location history
2006–2008Patents assigned to HITACHI ULSI SYS CO LTD (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
HITACHI LTD211990–2009
HITACHI VLSI ENG91990–2009
HITACHI ULSI SYS CO LTD32006–2008
HITACHI DEVICE ENG11999
HITACHI ULSI ENG CORP11999
Locations
LocationPatentsSpan
Tokyo, JP221990–2009
Kokubunji, JP12002
Musashino, JP11999