Inventor
Douglas Craig Bossen
Inventor
Austin, TX, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing59%
G06KGraphical data reading16%
H03MCoding9%
G11CStatic stores6%
H04LTransmission of digital information, e.g. telegraphic communication6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
6,851,071'Apparatus and method of repairing a processor array for a failure detected at runtime'20056,789,048'Method, apparatus, and computer program product for deconfiguring a processor'20046,675,341'Extended error correction for SEC-DED codes with package error detection ability'20046,636,981'Method and system for end-to-end problem determination and fault isolation for storage area networks'20036,516,429'Method and apparatus for run-time deconfiguration of a processor in a symmetrical multi-processing system'20036,332,181'Recovery mechanism for L1 data cache parity errors'20016,243,823'Method and system for boot-time deconfiguration of a memory in a processing system'20016,233,680'Method and system for boot-time deconfiguration of a processor in a symmetrical multi-processing system'20016,223,299'Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables'20016,199,171'Time-lag duplexing techniques'20016,179,207'Method for writing single width bar codes on semiconductors wafers'20016,108,753'Cache error retry technique'20006,058,491'Method and system for fault-handling to improve reliability of a data-processing system'20005,978,936'Run time error probe in a network computing environment'19995,956,351'Dual error correction code'19995,682,394'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19975,552,591'Presence/absence bar code'19965,533,036'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19965,521,709'Continuous barcode marking system'19965,380,998'Single width bar code with end code providing bidirectionality'19955,228,046'Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature'19935,161,163'Method and apparatus for providing error correction to symbol level codes'19925,058,115'Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature'19914,461,001'Deterministic permutation algorithm'19844,319,357'Double error correction using single error correcting code'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982–2005Patents assigned to IBM (25)· patent assignee history
1982–2001Based in Poughkeepsie, NY, US· patent location history
1995–2005Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 25 | 1982–2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 15 | 1995–2005 |
| Poughkeepsie, New York, US | 10 | 1982–2001 |