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Inventor

Edward D. Nowak

Inventor
Pleasanton, CA, US

Overview

17→
Patents
1993–2015
Patent span
Electricity
Primary field (CPC H)

Patents· 17 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices28%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
LOC148%
F16MFrames, casings or beds of engines, machines or apparatus, not specific to engines, machines or apparatus provided for elsewhere4%
F21VFunctional features or details of lighting devices or systems thereof4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G11CStatic stores4%
H01FMagnets4%
H10BElectronic memory devices4%
PatentTitleYear
8,979,044'Magnetic hold devices and systems'2015D0723203'Light'2015D0665757'Controller'2012D0662066'Controller'20126,226,782'Apparatus for automated pillar layout'20016,091,594'Protection circuits and methods of protecting a semiconductor device'20006,080,608'Polysilicon pillar heat sinks for semiconductor on insulator circuits'20006,013,536'Apparatus for automated pillar layout and method for implementing same'20005,793,107'Polysilicon pillar heat sinks for semiconductor on insulator circuits'19985,700,717'Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs'19975,597,668'Patterned filled photo mask generation for integrated circuit manufacturing'19975,516,707'Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor'19965,399,508'Method for self-aligned punchthrough implant using an etch-back gate'19955,400,277'Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches'19955,396,454'Static random access memory cell utilizing a gated diode load element'19955,288,652'BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure'19945,196,357'Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2000Patents assigned to VLSI TECHNOLOGY INC (12)· patent assignee history
1993–2001Based in Pleasanton, CA, US· patent location history
2012–2015Patents assigned to NOWAK EDWARD (4)· patent assignee history
2012–2015Patents assigned to RAFFEL SYSTEMS LLC (4)· patent assignee history
2012–2015Patents assigned to SEIDL KENNETH G (4)· patent assignee history
2012–2015Patents assigned to LI PAUL (2)· patent assignee history
2012–2015Based in West Bend, WI, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
VLSI TECHNOLOGY INC121993–2000
NOWAK EDWARDself42012–2015
RAFFEL SYSTEMS LLC42012–2015
SEIDL KENNETH G42012–2015
LI PAUL22012–2015
Locations
LocationPatentsSpan
Pleasanton, California, US131993–2001
West Bend, WI, US42012–2015