Inventor
Sreenivas Subramoney
Inventor
Bangalore, IN
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing75%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
G11CStatic stores6%
G06TImage data processing or generation, in general4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G06KGraphical data reading2%
G06VImage or video recognition or understanding2%
PatentTitleYear
11,080,194System, method, and apparatus for enhanced pointer identification and prefetching202111,043,256High bandwidth destructive read embedded memory202110,956,327Systems and methods for mitigating dram cache conflicts through hardware assisted redirection of pages (HARP)202110,949,208System, apparatus and method for context-based override of history-based branch predictions202110,915,421Technology for dynamically tuning processor features202110,866,902Memory aware reordered source202010,846,093System, apparatus and method for focused data value prediction to accelerate focused instructions202010,846,084Supporting timely and context triggered prefetching in microprocessors202010,776,270Memory-efficient last level cache architecture202010,754,655Automatic predication of hard-to-predict convergent branches202010,719,355Criticality based port scheduling202010,713,053Adaptive spatial access prefetcher apparatus and method202010,664,281Apparatuses and methods for dynamic asymmetric scaling of branch predictor tables202010,642,621System, apparatus and method for controlling allocations into a branch prediction circuit of a processor202010,579,414Misprediction-triggered local history-based branch prediction202010,559,348System, apparatus and method for simultaneous read and precharge of a memory202010,496,413Efficient hardware-based extraction of program instructions for critical paths201910,430,198Dynamic detection and prediction for store-dependent branches201910,423,422Branch predictor with empirical branch bias override201910,402,413Hardware accelerator for selecting data elements201910,331,582Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time201910,318,834Optimized image feature extraction201910,268,600System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor201910,191,689Systems and methods for page management using local page information201910,176,124Scoreboard approach to managing idle page close timeout duration in memory201910,162,756Memory-efficient last level cache architecture201810,013,352Partner-aware virtual microsectoring for sectored cache architectures20189,921,839'Coordinated thread criticality-aware memory scheduling'20189,720,829'Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level caches'20179,323,678'Identifying and prioritizing critical instructions within processor circuitry'20169,251,096'Data compression in processor caches'20169,195,606'Dead block predictors for cooperative execution in the last level cache'20158,667,222'Bypass and insertion algorithms for exclusive last-level caches'20147,577,947'Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects'20097,490,117'Dynamic performance monitoring-based approach to memory management'20097,389,385'Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis'20087,197,521'Method and system performing concurrently mark-sweep garbage collection invoking garbage collection thread to track and mark live objects in heap block using bit vector'20076,950,837'Method for using non-temporal streaming to improve garbage collection algorithm'20056,662,274'Method for using cache prefetch feature to improve garbage collection algorithm'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2021Patents assigned to INTEL CORP (39)· patent assignee history
2003–2009Based in Palo Alto, CA, US· patent location history
2014–2018Patents assigned to SUBRAMONEY SREENIVAS (4)· patent assignee history
2014–2017Patents assigned to GAUR JAYESH (2)· patent assignee history
2014Patents assigned to CHAUDHURI MAINAK (1)· patent assignee history
2014–2021Based in Bangalore, IN· patent location history
2018Patents assigned to BASHYAM NITHIYANANDAN (1)· patent assignee history
2018–2020Based in Bengaluru, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 39 | 2003–2021 |
| SUBRAMONEY SREENIVASself | 4 | 2014–2018 |
| GAUR JAYESH | 2 | 2014–2017 |
| BASHYAM NITHIYANANDAN | 1 | 2018 |
| CHAUDHURI MAINAK | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 31 | 2014–2021 |
| Palo Alto, California, US | 6 | 2003–2009 |
| Bengaluru, IN | 2 | 2018–2020 |