Inventor
William L. Devanney
Inventor
Menlo Park, CA, US
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores40%
G06FElectric digital data processing30%
H03KPulse technique20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
PatentTitleYear
6,763,406'Noise reduction system and method for reducing switching noise in an interface to a large width bus'20046,311,316'Designing integrated circuit gate arrays using programmable logic device bitstreams'20016,243,779'Noise reduction system and method for reducing switching noise in an interface to a large width bus'20016,225,652'Vertical laser fuse structure allowing increased packing density'20016,191,641'Zero power fuse circuit using subthreshold conduction'20015,910,922'Method for testing data retention in a static random access memory using isolated V.sub.cc supply'19995,541,883'Method and apparatus for simultaneous long writes of multiple cells of a row in a static ram'19965,440,524'Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2004Patents assigned to INTEGRATED DEVICE TECH (5)· patent assignee history
1995–1996Based in Pacific Grove, CA, US· patent location history
1999–2004Based in Menlo Park, CA, US· patent location history
2001Patents assigned to CLEAR LOGIC INC (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEGRATED DEVICE TECH | 5 | 1995–2004 |
| CLEAR LOGIC INC | 3 | 2001 |
Locations
| Location | Patents | Span |
|---|---|---|
| Menlo Park, California, US | 6 | 1999–2004 |
| Pacific Grove, California, US | 2 | 1995–1996 |