Inventor
Arvind Kumar
Inventor
Beaverton, OR, US
Overview
Patents· 185 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices17%
H10DInorganic electric semiconductor devices17%
G06FElectric digital data processing13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
H04LTransmission of digital information, e.g. telegraphic communication6%
H10BElectronic memory devices5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H04WWireless communication networks2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
PatentTitleYear
10,991,428Ternary content addressable memory202110,986,422Hyper video navigation202110,969,979Input/output (I/O) loopback function for I/O signaling testing202110,921,912Technologies for interfacing an input overlay device with a touch screen compute device202110,896,252Composite challenge task generation and deployment202110,825,821Cooling and power delivery for a wafer level computing board202010,761,641Dynamic on-demand joint processing of touch sensor data from multiple independent touch sensors at an electronic circuit202010,734,492Asymmetric high-k dielectric for reducing gate induced drain leakage202010,724,869Technologies for providing information to a user while traveling202010,727,232Dram and method of making202010,727,973Apparatus and method for self-learning and predictive DWDM network202010,707,224FinFET vertical flash memory2020D0888711Computer notebook202010,671,910Space-efficient dynamic addressing in very large sparse networks202010,672,907Channel region dopant control in fin field effect transistor202010,649,550Predictive detection of user intent for stylus use202010,613,754Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration202010,606,738Application testing on a blockchain202010,580,686Semiconductor structure with integrated passive structures202010,580,738Direct bonded heterogeneous integration packaging structures202010,566,058Ternary content addressable memory202010,546,809Wafer-scale power delivery202010,503,402Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration201910,496,309Input/output (I/O) loopback function for I/O signaling testing201910,452,602Apparatus for facilitating a connection with an external sensor module201910,446,606Back-side memory element with local memory select transistor201910,423,877High memory bandwidth neuromorphic computing system201910,381,452Asymmetric high-k dielectric for reducing gate induced drain leakage201910,374,048Asymmetric high-k dielectric for reducing gate induced drain leakage201910,367,072Asymmetric high-k dielectric for reducing gate induced drain leakage201910,338,701Active brush stylus2019D0847810Computer notebook2019D0846545Computer notebook201910,256,935Adaptive flexible grid in an optical network201910,248,591High performance interconnect201910,242,906Semiconductor structure with integrated passive structures201910,243,016Heterogeneous integration using wafer-to-wafer stacking with die size adjustment201910,236,317Heterogeneous integration using wafer-to-wafer stacking with die size adjustment201910,216,661High performance interconnect physical layer201910,204,685Ternary content addressable memory201910,201,312Opportunistic measurements and processing of user's context201910,204,909Non-uniform gate oxide thickness for DRAM device201910,192,161Lithium-drift based resistive processing unit for accelerating machine learning training201910,147,676Wafer-scale power delivery201810,145,694Technologies for providing information to a user while traveling201810,133,396Virtual input device using second touch-enabled display201810,049,942Asymmetric semiconductor device and method of forming same201810,032,862Semiconductor structure with integrated passive structures201810,025,981Visual object and event detection and prediction system using saccades2018D0822658Computer notebook201810,002,900Three-dimensional wafer scale integration of heterogeneous wafers with unequal die sizes201810,002,876FinFET vertical flash memory20189,991,167Method and IC structure for increasing pitch between gates20189,949,170Transmission modification20189,934,138Application testing on a blockchain20189,922,831'Asymmetric high-k dielectric for reducing gate induced drain leakage'20189,923,082'Junction butting structure using nonuniform trench shape'20189,904,341'Cascading power consumption'20189,892,086'High performance interconnect physical layer'20189,886,193'Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration'20189,881,956'Heterogeneous integration using wafer-to-wafer stacking with die size adjustment'20189,870,503'Visual object and event detection and prediction system using saccades'20189,859,122'Asymmetric high-k dielectric for reducing gate induced drain leakage'20189,848,302Self-learning locator for mobile device20179,837,319Asymmetric high-K dielectric for reducing gate induced drain leakage20179,817,054'Electrical margining of multi-parameter high-speed interconnect links with multi-sample probing'20179,768,071'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,768,195'Semiconductor structure with integrated passive structures'20179,753,557'Fast inking a touch display'20179,721,843'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,712,960'Geofencing'20179,703,301'Methods and control systems of resistance adjustment of resistors'20179,698,159'Semiconductor structure with integrated passive structures'20179,691,810'Curved image sensor'20179,685,379'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,673,197'FinFET with constrained source-drain epitaxial region'20179,659,961'Semiconductor structure with integrated passive structures'20179,660,105'Finfet crosspoint flash memory'20179,652,388'Method, apparatus and system for performing management component transport protocol (MCTP) communications with a universal serial bus (USB) device'20179,633,255'Substitution of handwritten text with a custom handwritten font'20179,627,480'Junction butting structure using nonuniform trench shape'20179,626,321'High performance interconnect'20179,619,538'Techniques for data integration'20179,577,061'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,570,354'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,565,405'Image sensor with enhanced quantum efficiency'20179,559,010'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,548,356'Shallow trench isolation structures'20179,543,213'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,544,419'Methods and systems for configuring a mobile device based on an orientation-based usage context'20179,536,879'FinFET with constrained source-drain epitaxial region'20179,524,986'Trapping dislocations in high-mobility fins below isolation layer'20169,508,826'Replacement gate structure for enhancing conductivity'20169,484,246'Buried signal transmission line'20169,455,291'Blue enhanced image sensor'20169,450,072'Replacement gate structure for enhancing conductivity'20169,448,663'Parallel touch point detection using processor graphics'20169,443,854'FinFET with constrained source-drain epitaxial region'20169,442,865'Processor extensions for execution of secure embedded containers'20169,436,295'Alternate dynamic keyboard for convertible tablet computers'20169,425,079'Semiconductor structure with integrated passive structures'20169,418,903'Structure and method for effective device width adjustment in finFET devices using gate workfunction shift'20169,412,759'CMOS gate contact resistance reduction'20169,412,667'Asymmetric high-k dielectric for reducing gate induced drain leakage'20169,400,511'Methods and control systems of resistance adjustment of resistors'20169,401,325'Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication'20169,379,185'Method of forming channel region dopant control in fin field effect transistor'20169,378,171'High performance interconnect physical layer'20169,311,512'Apparatus and method to harden computer system'20169,305,930'Finfet crosspoint flash memory'20169,299,780'Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device'20169,287,399'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20169,269,786'Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors'20169,268,594'Processor extensions for execution of secure embedded containers'20169,252,215'Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device'20169,240,431'Conductive trench isolation'20169,219,059'Semiconductor structure with integrated passive structures'20159,195,824'Providing integrity verification and attestation in a hidden execution environment'20159,190,313'Shallow trench isolation structures'20159,190,418'Junction butting in SOI transistor with embedded source/drain'20159,111,993'Conductive trench isolation'20159,104,793'Method and system of adapting communication links to link conditions on a platform'20159,086,913'Processor extensions for execution of secure embedded containers'20159,064,972'Method of forming a gated diode structure for eliminating RIE damage from cap removal'20159,059,243'Shallow trench isolation structures'20158,983,460'Sensor and context based adjustment of the operation of a network controller'20158,963,228'Non-volatile memory device integrated with CMOS SOI FET on a single chip'20158,940,595'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20158,941,189'Fin-shaped field effect transistor (finFET) structures having multiple threshold voltages (Vt) and method of forming'20158,942,333'Apparatus and methods for clock alignment for high speed interfaces'20158,896,560'Offloading touch processing to a graphics processor'20148,890,588'Circuits and methods for asymmetric aging prevention'20148,884,906'Offloading touch processing to a graphics processor'20148,887,267'Providing integrity verification and attestation in a hidden execution environment'20148,839,356'Methods and apparatuses for processing wake events of communication networks'20148,829,616'Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage'20148,816,473'Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication'20148,819,857'Apparatus and method to harden computer system'20148,779,551'Gated diode structure for eliminating RIE damage from cap removal'20148,737,161'Write-leveling system and method'20148,680,623'Techniques for enabling multiple Vt devices using high-K metal gate stacks'20148,673,738'Shallow trench isolation structures'20148,667,448'Integrated circuit having local maximum operating voltage'20148,558,313'Bulk substrate FET integrated on CMOS SOI'20138,510,569'Providing integrity verification and attestation in a hidden execution environment'20138,482,075'Structure and method for manufacturing asymmetric devices'20138,386,823'Method and apparatus for cost and power efficient, scalable operating system independent services'20138,343,781'Electrical mask inspection'20138,299,519'Read transistor for single poly non-volatile memory using body contacted SOI device'20128,239,452'System and method for discovering and publishing of presence information on a network'20128,232,599'Bulk substrate FET integrated on CMOS SOI'20128,232,151'Structure and method for manufacturing asymmetric devices'20128,212,322'Techniques for enabling multiple Vt devices using high-K metal gate stacks'20128,171,321'Method and apparatus for cost and power efficient, scalable operating system independent services'20128,132,267'Apparatus and method to harden computer system'20128,053,325'Body contact structures and methods of manufacturing the same'20118,034,692'Structure and method for manufacturing asymmetric devices'20118,030,145'Back-gated fully depleted SOI transistor'20117,956,415'SOI transistor having a carrier recombination structure in a body'20117,936,042'Field effect transistor containing a wide band gap semiconductor material in a drain'20117,838,942'Substrate solution for back gate controlled SRAM with coexisting logic devices'20107,802,083'Utilization based installation on a computing system'20107,718,496'Techniques for enabling multiple Vt devices using high-K metal gate stacks'20107,593,988'Systems and methods for multiparty session invite'20097,536,479'Local and remote network based management of an operating system-independent processor'20097,437,566'System and method for identity confirmation of a contact published on a network'20087,418,608'Method and an apparatus for managing power consumption of a server'20087,417,288'Substrate solution for back gate controlled SRAM with coexisting logic devices'20087,407,871'Method for passivation of plasma etch defects in DRAM devices'20087,389,342'Service creator apparatus, systems, and methods'20087,365,398'Compact SRAMs and other multiple transistor structures'20087,332,947'Method and apparatus for distorting duty cycle of a clock'20087,327,150'Integrated circuit package resistance measurement'20087,272,644'Internet based network topology discovery'20077,024,695'Method and apparatus for secure remote system management'20066,954,934'Management of links to data embedded in blocks of data'20056,854,122'Java common information model interface for windows management instrumentation via COM/DCOM'20056,668,335'System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths'20036,665,731'Method for remotely accessing component management information'20036,567,977'Method and apparatus for software program installation preview directed to system software'20036,534,819'Dense backplane cell for configurable logic'20036,445,032'Floating back gate electrically erasable programmable read-only memory(EEPROM)'20026,370,072'Low voltage single-input DRAM current-sensing amplifier'20026,337,497'Common source transistor capacitor stack'20026,248,626'Floating back gate electrically erasable programmable read-only memory (EEPROM)'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2021Patents assigned to IBM (91)· patent assignee history
2003–2021Patents assigned to INTEL CORP (59)· patent assignee history
2003–2021Based in Beaverton, OR, US· patent location history
2008–2021Based in Brookline, MA, US· patent location history
2010–2021Based in Chappaqua, NY, US· patent location history
2011–2020Based in Beacon, NY, US· patent location history
2011–2014Based in Hopewell Junction, NY, US· patent location history
2012–2018Patents assigned to KUMAR ARVIND (25)· patent assignee history
2012–2014Patents assigned to NARASIMHA SHREESH (5)· patent assignee history
2016–2018Patents assigned to GLOBALFOUNDRIES INC (14)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 91 | 2001–2021 |
| INTEL CORP | 59 | 2003–2021 |
| KUMAR ARVINDself | 25 | 2012–2018 |
| GLOBALFOUNDRIES INC | 14 | 2016–2018 |
| NARASIMHA SHREESH | 5 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 47 | 2003–2021 |
| Beacon, New York, US | 45 | 2011–2020 |
| Chappaqua, New York, US | 42 | 2010–2021 |
| Hopewell Junction, New York, US | 10 | 2011–2014 |
| Brookline, Massachusetts, US | 8 | 2008–2021 |