Inventor

Larisa Novakovsky

Inventor

Haifa, IL

Overview

23→

Patents

2011–2021

Patent span

Physics

Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing64%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%

G01RMeasuring electric variables6%

G06TImage data processing or generation, in general6%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%

G09GArrangements or circuits for control of indicating devices using static means to present variable information3%

G11CStatic stores3%

PatentTitleYear

11,048,512Apparatus and method to identify the source of an interrupt2021 10,990,534Device, system and method to facilitate disaster recovery for a multi-processor platform2021 10,775,434System, apparatus and method for probeless field scan of a processor2020 10,725,848Supporting hang detection and data recovery in microprocessor systems2020 10,719,326Communicating via a mailbox interface of a processor2020 10,628,542Core-only system management interrupt2020 10,175,992Systems and methods for enhancing BIOS performance by alleviating code-size limitations2019 10,157,136Pipelined prefetcher for parallel advancement of multiple data streams2018 9,990,287Apparatus and method for memory-hierarchy aware producer-consumer instruction2018 9,830,272Cache memory staged reopen2017 9,710,041'Masking a power state of a core of a processor'2017 9,684,595'Adaptive hierarchical cache policy in a microprocessor'2017 9,535,476'Apparatus and method to transfer data packets between domains of a processor'2017 9,471,088'Restricting clock signal delivery in a processor'2016 9,471,494'Method and apparatus for cache line write back operation'2016 9,448,879'Apparatus and method for implement a multi-level memory hierarchy'2016 9,378,148'Adaptive hierarchical cache policy in a microprocessor'2016 9,367,464'Cache circuit having a tag array with smaller latency than a data array'2016 9,360,924'Reduced power mode of a cache unit'2016 8,996,833'Multi latency configurable cache'2015 8,990,512'Method and apparatus for error correction in a cache'2015 8,347,035'Posting weakly ordered transactions'2013 7,958,510'Device, system and method of managing a resource request'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011–2021Patents assigned to INTEL CORP (23)· patent assignee history

2011–2021Based in Haifa, IL· patent location history

2013–2018Patents assigned to NOVAKOVSKY LARISA (6)· patent assignee history

2013–2016Patents assigned to MANDELBLAT JULIUS (2)· patent assignee history

2013–2018Patents assigned to RAIKIN SHLOMO (2)· patent assignee history

2013–2016Patents assigned to SANTHANAKRISHNAN GEEYARPURAM N (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	23	2011–2021
NOVAKOVSKY LARISAself	6	2013–2018
MANDELBLAT JULIUS	2	2013–2016
RAIKIN SHLOMO	2	2013–2018
SANTHANAKRISHNAN GEEYARPURAM N	2	2013–2016

Locations

Location	Patents	Span
Haifa, IL	23	2011–2021