LexDanaLexDanabeta
Inventor

Raminda Udaya Madurawe

Inventor
Sunnyvale, CA, US

Overview

142→
Patents
1992–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 142 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique23%
H10DInorganic electric semiconductor devices20%
G11CStatic stores18%
H10BElectronic memory devices14%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H01LSemiconductor devices6%
G06FElectric digital data processing4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H04NPictorial communication, e.g. television2%
PatentTitleYear
11,133,346Stacked-die image sensors with shielding202110,964,705Method of forming a semiconductor device202110,708,529Image sensors with low-voltage transistors202010,594,320Programmable structured arrays202010,566,375Stacked-die image sensors with shielding202010,447,272Three dimensional integrated-circuits201910,339,245Timing exact design conversions from FPGA to ASIC201910,304,854Pads and pin-outs in three dimensional integrated circuits201910,033,947Multi-port image pixels20189,978,773Pads and pin-outs in three dimensional integrated circuits20189,912,336'Three dimensional integrated circuits'20189,882,567'Programmable structured arrays'20189,812,555'Bottom-gate thin-body transistors for stacked wafer integrated circuits'20179,686,457'High efficiency image sensor pixels with deep trench isolation structures and embedded reflectors'20179,679,914'Pads and pin-outs in three dimensional integrated circuits'20179,591,245'Image sensor pixels with adjustable body bias'20179,564,464'Monolithically stacked image sensors'20179,547,736'Timing exact design conversions from FPGA to ASIC'20179,524,994'Image sensor pixels with multiple compartments'20169,397,665'Programmable structured arrays'20169,240,790'Three dimensional integrated circuits'20169,087,169'Automated metal pattern generation for integrated circuits'20159,070,668'Pads and pin-outs in three dimensional integrated circuits'20158,856,699'Three dimensional integrated circuits'20148,829,664'Three dimensional integrated circuits'2014RE045110'MPGA products based on a prototype FPGA'20148,810,276'Programmable structured arrays'20148,643,162'Pads and pin-outs in three dimensional integrated circuits'20148,499,269'Timing exact design conversions from FPGA to ASIC'20138,429,585'Three dimensional integrated circuits'20138,274,309'Programmable structured arrays'20128,230,375'Automated metal pattern generation for integrated circuits'20128,159,265'Memory for metal configurable integrated circuits'20128,159,266'Metal configurable integrated circuits'20128,159,268'Interconnect structures for metal configurable integrated circuits'20127,812,458'Pad invariant FPGA and ASIC devices'20107,777,319'Three dimensional integrated circuits'20107,759,705'Semiconductor devices fabricated with different processing options'20107,759,969'Programmable logic devices comprising time multiplexed programmable interconnect'20107,709,314'Semiconductor switching devices and fabrication methods'20107,679,399'Programmable interconnect structures'20107,673,273'MPGA products based on a prototype FPGA'20107,656,190'Incrementer based on carry chain compression'20107,656,192'Three dimensional integrated circuits'20107,635,988'Multi-port thin-film memory devices'20097,627,848'Bit stream compatible FPGA to MPGA conversions'20097,573,294'Programmable logic based latches and shift registers'20097,573,293'Programmable logic based latches and shift registers'20097,538,575'Three dimensional integrated circuits'20097,489,164'Multi-port memory devices'20097,486,111'Programmable logic devices comprising time multiplexed programmable interconnect'20097,466,163'Look-up table structure with embedded carry logic'20087,463,059'Alterable application specific integrated circuit (ASIC)'20087,446,563'Three dimensional integrated circuits'20087,362,133'Three dimensional integrated circuits'20087,356,799'Timing exact design conversions from FPGA to ASIC'20087,345,505'Alterable application specific integrated circuit (ASIC)'20087,336,097'Look-up table structure with embedded carry logic'20087,332,934'Programmable interconnect structures'20087,323,905'Programmable structured arrays'20087,312,109'Methods for fabricating fuse programmable three dimensional integrated circuits'20077,298,641'Configurable storage device'20077,285,981'Configuration circuit for programmable logic devices'20077,285,982'Configuration circuits for programmable logic devices'20077,285,984'Look-up table structure with embedded carry logic'20077,268,580'Configuration circuits for three dimensional programmable logic devices'20077,265,421'Insulated-gate field-effect thin film transistors'20077,265,577'Integrated circuits with RAM and ROM fabrication options'20077,253,659'Field programmable structured arrays'20077,239,175'Look-up table based logic macro-cells'20077,239,174'Programmable interconnect structures'20077,208,976'Look-up table based logic macro-cells'20077,205,589'Semiconductor devices fabricated with different processing options'20077,176,713'Integrated circuits with RAM and ROM fabrication options'20077,176,716'Look-up table structure with embedded carry logic'20077,129,744'Programmable interconnect structures'20067,112,994'Three dimensional integrated circuits'20067,084,666'Programmable interconnect structures'20067,071,104'Laser alignment target'20067,064,579'Alterable application specific integrated circuit (ASIC)'20067,064,018'Methods for fabricating three dimensional integrated circuits'20067,042,756'Configurable storage device'20067,030,651'Programmable structured arrays'20067,030,446'Semiconductor switching devices'20067,019,557'Look-up table based logic macro-cells'20067,018,875'Insulated-gate field-effect thin film transistors'20066,998,722'Semiconductor latches and SRAM devices'20066,992,503'Programmable devices with convertibility to customizable devices'20066,972,234'High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage'20056,856,030'Semiconductor latches and SRAM devices'20056,855,988'Semiconductor switching devices'20056,849,958'Semiconductor latches and SRAM devices'20056,828,689'Semiconductor latches and SRAM devices'20046,828,620'Nonvolatile memory cell with low doping region'20046,803,804'Programmable latch array using antifuses'20046,781,883'Apparatus and method for margin testing single polysilicon EEPROM cells'20046,747,478'Field programmable gate array with convertibility to application specific integrated circuit'20046,713,839'Antifuse structure with low resistance'20046,646,919'Apparatus and method for margin testing single polysilicon EEPROM cells'20036,624,524'Laser alignment target'20036,624,467'EEPROM active area castling'20036,573,138'Nonvolatile memory cell with low doping region'20036,532,170'Nonvolatile configuration cells and cell arrays'20036,472,272'Castled active area mask'20026,417,550'High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage'20026,366,498'Nonvolatile configuration cells and cell arrays'20026,295,230'Nonvolatile configuration cells and cell arrays'20016,268,623'Apparatus and method for margin testing single polysilicon EEPROM cells'20016,265,746'Highly resistive interconnects'20016,226,201'Techniques to configure nonvolatile cells and cell arrays'20016,187,634'Process for making an EEPROM active area castling'20016,127,217'Method of forming highly resistive interconnects'20006,122,209'Method of margin testing programmable interconnect cell'20006,108,239'High-density nonvolatile memory cell'20006,091,102'High-density nonvolatile memory cell'20006,081,449'High-density nonvolatile memory cell'20006,078,521'Nonvolatile configuration cells and cell arrays'20006,052,309'Nonvolatile configuration cells and cell arrays'20006,028,787'Nonvolatile static memory circuit'20006,018,476'Nonvolatile configuration cells and cell arrays'20006,005,806'Nonvolatile configuration cells and cell arrays'19996,002,182'Laser alignment target'19995,998,295'Method of forming a rough region on a substrate'19995,998,263'High-density nonvolatile memory cell'19995,949,250'Two-terminal electrically-reprogrammable programmable logic element'19995,949,710'Programmable interconnect junction'19995,943,267'High-density nonvolatile memory cell'19995,939,790'Integrated circuit pad structures'19995,925,904'Two-terminal electrically-reprogrammable programmable logic element'19995,914,509'Two-terminal electrically-reprogrammable programmable logic element'19995,905,675'Biasing scheme for reducing stress and improving reliability in EEPROM cells'19995,898,630'Dynamic nonvolatile memory cell'19995,812,450'Nonvolatile SRAM cells and cell arrays'19985,805,516'Dynamic nonvolatile memory cell'19985,740,110'Dynamic nonvolatile memory cell'19985,729,495'Dynamic nonvolatile memory cell'19985,696,455'Reconfigurable programmable logic device'19975,581,501'Nonvolatile SRAM cells and cell arrays'19965,548,552'Reconfigurable programmable logic device'19965,548,228'Reconfigurable programmable logic device having static and non-volatile memory'19965,488,586'Method and apparatus for erasing an array of electrically erasable programmable read only memory cells'19965,138,576'Method and apparatus for erasing an array of electrically erasable EPROM cells'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2006Patents assigned to ALTERA CORP (47)· patent assignee history
1992Based in Santa Clara, CA, US· patent location history
1996–2021Based in Sunnyvale, CA, US· patent location history
2005–2008Patents assigned to VICICIV TECHNOLOGY (29)· patent assignee history
2008–2010Patents assigned to TIER LOGIC INC (17)· patent assignee history
2009–2014Patents assigned to MADURAWE RAMINDA UDAYA (11)· patent assignee history
2016–2020Patents assigned to CALLAHAN CELLULAR LLC (11)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP471992–2006
VICICIV TECHNOLOGY292005–2008
TIER LOGIC INC172008–2010
CALLAHAN CELLULAR LLC112016–2020
MADURAWE RAMINDA UDAYAself112009–2014
Locations
LocationPatentsSpan
Sunnyvale, California, US1411996–2021
Santa Clara, California, US11992