Inventor
Eric R. Keller
Inventor
Boulder, CO, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
H04LTransmission of digital information, e.g. telegraphic communication21%
H03KPulse technique16%
G11CStatic stores5%
H04WWireless communication networks2%
PatentTitleYear
10,425,348Stateless network functions201910,223,139Dynamically deployable wireless infrastructure in cloud environment20198,806,032'Methods and apparatus to migrate border gateway protocol sessions between routers'20148,284,772'Method for scheduling a network packet processor'20128,065,130'Method for message processing on a programmable logic device'20118,032,874'Generation of executable threads having source code specifications that describe network packets'20117,990,867'Pipeline for processing network packets'20117,823,162'Thread circuits and a broadcast channel in programmable logic'20107,792,117'Method for simulating a processor of network packets'20107,788,402'Circuit for modification of a network packet by insertion or removal of a data segment'20107,784,014'Generation of a specification of a network packet processor'20107,770,179'Method and apparatus for multithreading on a programmable logic device'20107,698,449'Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element'20107,689,726'Bootable integrated circuit device for readback encoding of configuration data'20107,653,895'Memory arrangement for message processing by a plurality of threads'20107,574,680'Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip'20097,552,042'Method for message processing on a programmable logic device'20097,386,826'Using redundant routing to reduce susceptibility to single event upsets in PLD designs'20087,328,335'Bootable programmable logic device for internal decoding of encoded configuration data'20087,227,378'Reconfiguration of a programmable logic device using internal control'20077,228,520'Method and apparatus for a programmable interface of a soft platform on a programmable logic device'20077,185,309'Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip'20077,131,077'Using an embedded processor to implement a finite state machine'20067,111,215'Methods of reducing the susceptibility of PLD designs to single event upsets'20067,076,596'Method of and apparatus for enabling a hardware module to interact with a data structure'20067,028,283'Method of using a hardware library in a programmable logic device'20067,010,664'Configurable address generator and circuit using same'20066,920,627'Reconfiguration of a programmable logic device using internal control'20056,883,147'Method and system for generating a circuit design including a peripheral component connected to a bus'20056,725,441'Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices'20046,487,709'Run-time routing for programmable logic devices'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2012Patents assigned to XILINX INC (28)· patent assignee history
2002–2012Based in Boulder, CO, US· patent location history
2011–2012Patents assigned to JAMES-ROXBY PHILIP B (2)· patent assignee history
2011–2012Patents assigned to KELLER ERIC R (2)· patent assignee history
2011Patents assigned to BREBNER GORDON J (1)· patent assignee history
2014Patents assigned to AT & T IP I LP (1)· patent assignee history
2014Based in Ewing, NJ, US· patent location history
2019Based in Louisville, CO, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 28 | 2002–2012 |
| JAMES-ROXBY PHILIP B | 2 | 2011–2012 |
| KELLER ERIC Rself | 2 | 2011–2012 |
| AT & T IP I LP | 1 | 2014 |
| BREBNER GORDON J | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boulder, CO, US | 28 | 2002–2012 |
| Louisville, CO, US | 2 | 2019 |
| Ewing, New Jersey, US | 1 | 2014 |