Inventor
Masahiko Fujisawa
Inventor
Tokyo, JP
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10DInorganic electric semiconductor devices23%
H01LSemiconductor devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
B29CShaping or joining of plastics5%
C22CAlloys5%
H10BElectronic memory devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
C23CCoating metallic material2%
PatentTitleYear
10,475,883Semiconductor device and method of manufacturing thereof20199,738,014'Resin molding machine'20179,607,956'Semiconductor device and method of manufacturing the same'20179,406,628'Semiconductor device and method of manufacturing the same'20169,238,314'Method for resin molding and resin molding apparatus'20168,169,080'Semiconductor device and method of manufacture thereof'20127,906,848'Semiconductor device'20117,884,011'Semiconductor device and method of manufacture thereof'20117,714,413'Semiconductor device and method of manufacture thereof'20106,780,769'Method of manufacturing structure for connecting interconnect lines including metal layer with thickness larger than thickness of metallic compound layer'20046,716,731'Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate'20046,664,641'Wiring structure for an integrated circuit'20036,657,265'Semiconductor device and its manufacturing method'20036,624,516'Structure for connecting interconnect lines with interposed layer including metal layers and metallic compound layer'20036,593,217'Method of manufacturing semiconductor device'20036,472,700'Semiconductor device with isolation insulator, interlayer insulation film, and a sidewall coating film'20026,236,090'Semiconductor device and method for reducing contact resistance between an electrode and a semiconductor substrate'20015,565,708'Semiconductor device comprising composite barrier layer'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2003Patents assigned to MITSUBISHI ELECTRIC CORP (7)· patent assignee history
1996–2003Based in Hyogo, JP· patent location history
2001–2019Based in Tokyo, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (3)· patent assignee history
2011–2019Patents assigned to RENESAS ELECTRONICS CORP (6)· patent assignee history
2011Based in Takarazuka, JP· patent location history
2012–2017Patents assigned to FUJISAWA MASAHIKO (2)· patent assignee history
2016–2017Patents assigned to APIC YAMADA CORP (2)· patent assignee history
2016–2017Based in Chikuma, JP· patent location history
2016–2017Based in Kanagawa, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELECTRIC CORP | 7 | 1996–2003 |
| RENESAS ELECTRONICS CORP | 6 | 2011–2019 |
| RENESAS TECH CORP | 3 | 2004–2010 |
| APIC YAMADA CORP | 2 | 2016–2017 |
| FUJISAWA MASAHIKOself | 2 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 10 | 2001–2019 |
| Hyogo, JP | 3 | 1996–2003 |
| Chikuma, JP | 2 | 2016–2017 |
| Kanagawa, JP | 2 | 2016–2017 |
| Takarazuka, JP | 1 | 2011 |