Inventor
David L. O'Meara
Inventor
Albany, NY, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices18%
H01LSemiconductor devices13%
C23CCoating metallic material11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H01JElectric discharge tubes or discharge lamps5%
H10BElectronic memory devices4%
B82YSpecific uses or applications of nanostructures3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems2%
PatentTitleYear
11,024,535Method for filling recessed features in semiconductor devices with a low-resistivity metal202110,978,307Deposition process202110,964,587Atomic layer deposition for low-K trench protection during etch202110,770,294Selective atomic layer deposition (ALD) of protective caps to enhance extreme ultra-violet (EUV) etch resistance202010,734,228Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processes202010,700,009Ruthenium metal feature fill for interconnects202010,580,650Method for bottom-up formation of a film in a recessed feature202010,079,151Method for bottom-up deposition of a film in a recessed feature20189,899,224'Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions'20189,831,099Method and apparatus for multi-film deposition and etching in a batch processing system20179,443,731'Material processing to achieve sub-10nm patterning'20169,171,736'Spacer material modification to improve K-value and etch properties'20158,809,169'Multi-layer pattern for alternate ALD processes'20148,785,310'Method of forming conformal metal silicide films'20148,673,725'Multilayer sidewall spacer for seam protection of a patterned structure'20148,664,102'Dual sidewall spacer for seam protection of a patterned structure'20148,460,945'Method for monitoring status of system components'20137,509,962'Method and control system for treating a hafnium-based dielectric processing system'20097,501,352'Method and system for forming an oxynitride layer'20097,479,454'Method and processing system for monitoring status of system components'20097,470,591'Method of forming a gate stack containing a gate dielectric layer having reduced metal content'20087,235,440'Formation of ultra-thin oxide layers by self-limiting interfacial oxidation'20077,202,186'Method of forming uniform ultra-thin oxynitride layers'20077,141,765'Heat treating device'20066,974,779'Interfacial oxidation process for high-k gate dielectric process integration'20056,686,633'Semiconductor device, memory cell, and processes for forming them'20046,362,071'Method for forming a semiconductor device with an opening in a dielectric layer'20026,344,403'Memory device and method for manufacture'20026,320,784'Memory cell and method for programming thereof'20016,297,173'Process for forming a semiconductor device'20016,297,095'Memory device that includes passivated nanoclusters and method for manufacture'20016,184,073'Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or region'20015,972,804'Process for forming a semiconductor device'19995,013,690'Method for deposition of silicon films from azidosilane sources'19914,992,299'Deposition of silicon nitride films from azidosilane sources'19914,992,306'Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources'19914,981,724'Deposition of silicon oxide films using alkylsilane liquid sources'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991Based in Oceanside, CA, US· patent location history
1999–2004Patents assigned to MOTOROLA INC (8)· patent assignee history
1999–2004Based in Austin, TX, US· patent location history
2005–2014Patents assigned to IBM (6)· patent assignee history
2005–2014Based in Poughkeepsie, NY, US· patent location history
2006–2021Patents assigned to TOKYO ELECTRON LTD (22)· patent assignee history
2006Based in Hopewell Junction, NY, US· patent location history
2013–2014Patents assigned to O'MEARA DAVID L (5)· patent assignee history
2014Patents assigned to MOSDEN AELAN (3)· patent assignee history
2014–2021Based in Albany, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOKYO ELECTRON LTD | 22 | 2006–2021 |
| MOTOROLA INC | 8 | 1999–2004 |
| IBM | 6 | 2005–2014 |
| O'MEARA DAVID Lself | 5 | 2013–2014 |
| MOSDEN AELAN | 3 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Albany, New York, US | 13 | 2014–2021 |
| Poughkeepsie, New York, US | 11 | 2005–2014 |
| Austin, Texas, US | 8 | 1999–2004 |
| Oceanside, California, US | 4 | 1991 |
| Hopewell Junction, New York, US | 1 | 2006 |