Inventor
Jaynal A. Molla
Inventor
Gilbert, AZ, US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H01LSemiconductor devices16%
H05KPrinted circuits14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10TTechnical subjects covered by former us classification6%
G11CStatic stores5%
H01RElectrically-conductive connections5%
H10BElectronic memory devices5%
H10NElectric solid-state devices not otherwise provided for3%
B23KSoldering or unsoldering3%
PatentTitleYear
11,128,268Power amplifier packages containing peripherally-encapsulated dies and methods for the fabrication thereof202110,923,451Semiconductor dies having ultra-thin wafer backmetal systems, microelectronic devices containing the same, and associated fabrication methods202110,861,764Microelectronic components having integrated heat dissipation posts and systems including the same202010,825,747Semiconductor device package and methods of manufacture thereof202010,741,446Method of wafer dicing for wafers with backside metallization and packaged dies202010,727,153Thick-silver layer interface202010,529,638Molded air cavity packages and methods for the production thereof202010,485,091Microelectronic modules with sinter-bonded heat dissipation structures and methods for the fabrication thereof201910,431,449Microelectronic systems containing embedded heat dissipation structures and methods for the fabrication thereof201910,396,006Molded air cavity packages and methods for the production thereof201910,269,678Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof201910,199,303Molded air cavity packages and methods for the production thereof201910,199,302Molded air cavity packages and methods for the production thereof201910,141,182Microelectronic systems containing embedded heat dissipation structures and methods for the fabrication thereof20189,941,210Semiconductor devices with protruding conductive vias and methods of making such devices20189,922,894'Air cavity packages and methods for the production thereof'20189,875,987Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices20189,799,580'Semiconductor device package and methods of manufacture thereof'20179,698,116'Thick-silver layer interface for a semiconductor die and corresponding thermal layer'20179,589,860'Electronic devices with semiconductor die coupled to a thermally conductive substrate'20179,538,659'Solder wettable flanges and devices and systems incorporating solder wettable flanges'20179,425,161'Semiconductor device with mechanical lock features between a semiconductor die and a substrate'20169,099,567'Packaged semiconductor devices and methods of their fabrication'20157,829,980'Magnetoresistive device and method of packaging same'20107,598,596'Methods and apparatus for a dual-metal magnetic shield structure'20097,402,529'Method of applying cladding material on conductive lines of MRAM devices'20087,279,341'Method for fabricating a flux concentrating system for use in a magnetoelectronics device'20077,105,363'Cladded conductor for use in a magnetoelectronics device and method for fabricating the same'20066,943,038'Method for fabricating a flux concentrating system for use in a magnetoelectronics device'20056,936,763'Magnetic shielding for electronic circuits which include magnetic materials'20056,927,072'Method of applying cladding material on conductive lines of MRAM devices'20056,885,074'Cladded conductor for use in a magnetoelectronics device and method for fabricating the same'20056,517,698'System and method for providing rotation to plating flow'20036,414,509'Method and apparatus for in-situ testing of integrated circuit chips'20026,362,089'Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed'20026,150,255'Method of planarizing a curved substrate and resulting structure'20006,137,213'Field emission device having a vacuum bridge focusing structure and method'20006,043,150'Method for uniform plating of dendrites'20005,994,910'Apparatus, and corresponding method, for stress testing wire bond-type semi-conductor chips'19995,940,729'Method of planarizing a curved substrate and resulting structure'19995,939,786'Uniform plating of dendrites'19995,910,641'Selectively filled adhesives for compliant, reworkable, and solder-free flip chip interconnection and encapsulation'19995,813,870'Selectively filled adhesives for semiconductor chip interconnection and encapsulation'19985,798,050'Process for fabrication of a selectively filled flexible adhesive device for solderless connection of electronic modules to a substrate'19985,759,046'Dendritic interconnection system'19985,435,057'Interconnection method and structure for organic circuit boards'19955,432,998'Method of solder bonding processor package'19955,298,685'Interconnection method and structure for organic circuit boards'19945,237,743'Method of forming a conductive end portion on a flexible circuit member'19935,185,073'Method of fabricating nendritic materials'19935,137,461'Separable electrical connection technology'19924,894,296'Cathode for zinc air cells'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1990Based in Santa Clara, CA, US· patent location history
1992–2002Patents assigned to IBM (16)· patent assignee history
1992–2002Based in Endicott, NY, US· patent location history
1998–2000Based in Chandler, AZ, US· patent location history
2000–2021Based in Gilbert, AZ, US· patent location history
2005–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (13)· patent assignee history
2015–2017Patents assigned to MOLLA JAYNAL A (4)· patent assignee history
2015–2017Patents assigned to VISWANATHAN LAKSHMINARAYAN (4)· patent assignee history
2017–2021Patents assigned to NXP USA INC (21)· patent assignee history
2017Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NXP USA INC | 21 | 2017–2021 |
| IBM | 16 | 1992–2002 |
| FREESCALE SEMICONDUCTOR INC | 13 | 2005–2018 |
| MOLLA JAYNAL Aself | 4 | 2015–2017 |
| VISWANATHAN LAKSHMINARAYAN | 4 | 2015–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Gilbert, AZ, US | 34 | 2000–2021 |
| Endicott, New York, US | 8 | 1992–2002 |
| Chandler, AZ, US | 8 | 1998–2000 |
| Austin, Texas, US | 1 | 2017 |
| Santa Clara, California, US | 1 | 1990 |