Inventor
Subramanian Ramesh
Inventor
Cupertino, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices19%
G11CStatic stores18%
H10DInorganic electric semiconductor devices18%
G06FElectric digital data processing16%
H03KPulse technique7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G06NComputing arrangements based on specific computational models1%
H04NPictorial communication, e.g. television1%
PatentTitleYear
10,878,124Systems and methods for detecting sensitive information using pattern recognition20209,465,954'Method and system for tracking masking of data'20169,268,947'Method and system for managing information associated with sensitive information in an enterprise'20168,429,586'Basic cell architecture for structured ASICs'20138,178,909'Integrated circuit cell architecture configurable for memory or logic elements'20128,166,440'Basic cell architecture for structured application-specific integrated circuits'20128,044,437'Integrated circuit cell architecture configurable for memory or logic elements'20117,869,251'SRAM based one-time-programmable memory'20117,440,356'Modular design of multiport memory bitcells'20087,404,154'Basic cell architecture for structured application-specific integrated circuits'20087,114,064'System and method for accessing an advanced configuration and power interface (ACPI) namespace nodal tree'20067,006,370'Memory cell architecture'20067,007,160'System and method for loading an advanced configuration and power interface (ACPI) original equipment manufacturer (OEM) description table'20067,006,369'Design and use of a spacer cell to support reconfigurable memories'20066,980,462'Memory cell architecture for reduced routing congestion'20056,977,512'Method and apparatus for characterizing shared contacts in high-density SRAM cell design'20056,978,407'Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory'20056,963,970'System and method for executing a fast reset of a computer system'20056,934,174'Reconfigurable memory arrays'20056,865,614'Method for transferring a packed data structure to an unpacked data structure by copying the packed data using pointer'20056,778,462'Metal-programmable single-port SRAM array for dual-port functionality'20046,413,848'Self-aligned fuse structure and method with dual-thickness dielectric'20026,388,586'Method for reversing the bits of a computer data structure'20026,259,146'Self-aligned fuse structure and method with heat sink'20016,218,276'Silicide encapsulation of polysilicon gate and interconnect'20016,166,403'Integrated circuit having embedded memory with electromagnetic shield'20006,162,714'Method of forming thin polygates for sub quarter micron CMOS process'20006,066,525'Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process'20006,061,264'Self-aligned fuse structure and method with anti-reflective coating'20006,037,233'Metal-encapsulated polysilicon gate and interconnect'20005,953,614'Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step'19994,888,302'Method of reduced stress recrystallization'19894,795,679'Monocrystalline silicon layers on substrates'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989Based in Ossining, NY, US· patent location history
1999–2011Patents assigned to LSI LOGIC CORP (17)· patent assignee history
1999–2013Based in Cupertino, CA, US· patent location history
2002–2006Based in Plano, TX, US· patent location history
2005–2006Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (4)· patent assignee history
2008–2013Patents assigned to LSI CORP (6)· patent assignee history
2012–2013Patents assigned to RAMESH SUBRAMANIAN (3)· patent assignee history
2016–2020Patents assigned to DATAGUISE INC (3)· patent assignee history
2016Based in San Jose, CA, US· patent location history
2020Based in Fremont, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 17 | 1999–2011 |
| LSI CORP | 6 | 2008–2013 |
| HEWLETT PACKARD DEVELOPMENT CO | 4 | 2005–2006 |
| DATAGUISE INC | 3 | 2016–2020 |
| RAMESH SUBRAMANIANself | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 23 | 1999–2013 |
| Plano, Texas, US | 5 | 2002–2006 |
| San Jose, California, US | 2 | 2016 |
| Ossining, New York, US | 2 | 1989 |
| Fremont, California, US | 1 | 2020 |