Inventor
Matthew W. Stoker
Inventor
Poughkeepsie, NY, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices47%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
B82YSpecific uses or applications of nanostructures6%
H10BElectronic memory devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,910,471Device with large EPI in FinFETs and method of manufacturing202110,529,831Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging202010,396,078Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same201910,204,984Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicide201910,121,706Semiconductor structure including two-dimensional and three-dimensional bonding materials201810,020,307Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same20189,673,295'Contact resistance optimization via EPI growth engineering'20179,287,399'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20169,236,477'Graphene transistor with a sublithographic channel width'20169,190,406'Fin field effect transistors having heteroepitaxial channels'20158,940,595'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20158,779,525'Method for growing strain-inducing materials in CMOS circuits in a gate first flow'20148,618,617'Field effect transistor device'20138,492,234'Field effect transistor device'20138,426,265'Method for growing strain-inducing materials in CMOS circuits in a gate first flow'20138,361,859'Stressed transistor with improved metastability'20137,932,189'Process of forming an electronic device including a layer of discontinuous storage elements'20117,928,502'Transistor devices with nano-crystal gate structures'20117,700,438'MOS device with nano-crystal gate structure'20107,683,443'MOS devices with multi-layer gate stack'20107,510,956'MOS device with multi-layer gate stack'20097,238,580'Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration'20077,029,980'Method of manufacturing SOI template layer'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2011Patents assigned to FREESCALE SEMICONDUCTOR INC (6)· patent assignee history
2006–2011Based in Mesa, AZ, US· patent location history
2013–2021Patents assigned to GLOBALFOUNDRIES INC (12)· patent assignee history
2013–2016Patents assigned to IBM (8)· patent assignee history
2013Patents assigned to DUBE ABHISHEK (3)· patent assignee history
2013Patents assigned to HOLT JUDSON R (3)· patent assignee history
2013–2016Based in Poughkeepsie, NY, US· patent location history
2013–2014Based in Hopewell Junction, NY, US· patent location history
2018–2021Based in Ballston Lake, NY, US· patent location history
2019Based in Lake Placid, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 12 | 2013–2021 |
| IBM | 8 | 2013–2016 |
| FREESCALE SEMICONDUCTOR INC | 6 | 2006–2011 |
| DUBE ABHISHEK | 3 | 2013 |
| HOLT JUDSON R | 3 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 7 | 2013–2016 |
| Mesa, AZ, US | 6 | 2006–2011 |
| Ballston Lake, New York, US | 5 | 2018–2021 |
| Hopewell Junction, New York, US | 2 | 2013–2014 |
| Lake Placid, New York, US | 1 | 2019 |