Inventor
Alireza S. Kaviani
Inventor
San Jose, CA, US
Overview
Patents· 38 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique44%
G06FElectric digital data processing25%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses21%
H04LTransmission of digital information, e.g. telegraphic communication4%
G11CStatic stores2%
H03DDemodulation or transference of modulation from one carrier to another2%
H04BTransmission2%
PatentTitleYear
10,498,567Die-to-die communications scheme201910,042,806System-level interconnect ring for a programmable integrated circuit201810,002,100Active-by-active programmable device20189,875,330Folding duplicate instances of modules in a circuit design20189,602,108'Lut cascading circuit'20178,938,700'Data-driven pattern matching in synthesis of circuit designs'20158,913,601'Programmable integrated circuit and method of asynchronously routing data in a circuit block of an integrated circuit'20148,831,064'Method of and circuit for generating a spread spectrum clock signal'20148,788,553'Method and circuit for providing digital frequency synthesis'20148,358,148'Programmable integrated circuit and method of asynchronously routing data in an integrated circuit'20138,294,490'Integrated circuit and method of asynchronously routing data in an integrated circuit'20127,479,814'Circuit for digital frequency synthesis in an integrated circuit'20097,477,112'Structure for the main oscillator of a counter-controlled delay line'20097,453,297'Method of and circuit for deskewing clock signals in an integrated circuit'20087,453,301'Method of and circuit for phase shifting a clock signal'20087,236,026'Circuit for and method of generating a frequency aligned clock signal'20077,190,756'Hybrid counter with an asynchronous front end'20077,190,196'Dual-edge synchronized data sampler'20077,071,751'Counter-controlled delay line'20066,978,427'Literal sharing method for fast sum-of-products logic'20056,943,597'Hard phase alignment of clock signals with an oscillator controller'20056,914,449'Structure for reducing leakage current in submicron IC devices'20056,873,183'Method and circuit for glitchless clock control'20056,847,246'Method and apparatus for reducing jitter and power dissipation in a delay line'20056,838,918'Hard phase alignment of clock signals using asynchronous level-mode state machine'20056,838,919'DCVSL pulse width controller and system'20056,806,732'FPGA with improved structure for implementing large multiplexers'20046,788,124'Method and apparatus for reducing jitter in a delay line and a trim unit'20046,784,692'FPGA with improved structure for implementing large multiplexers'20046,756,822'Phase detector employing asynchronous level-mode sequential circuitry'20046,754,686'Literal sharing method for fast sum-of-products logic'20046,603,332'Configurable logic block for PLD with logic gate for combining output with another configurable logic block'20036,556,042'FPGA with improved structure for implementing large multiplexers'20036,480,023'Configurable logic block for PLD'20026,466,052'Implementing wide multiplexers in an FPGA using a horizontal chain structure'20026,212,670'Method for implementing a programmable logic device having look-up table and product-term circuitry'20016,140,839'Computational field programmable architecture'20005,841,295'Hybrid programmable logic device'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998Patents assigned to HEWLETT PACKARD CO (1)· patent assignee history
1998–2001Based in Toronto, CA· patent location history
2001Patents assigned to AGILENT TECHNOLOGIES INC (1)· patent assignee history
2002–2019Patents assigned to XILINX INC (35)· patent assignee history
2002–2019Based in San Jose, CA, US· patent location history
2012–2014Patents assigned to KAVIANI ALIREZA S (5)· patent assignee history
2014Patents assigned to LEE TED (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| XILINX INC | 35 | 2002–2019 |
| KAVIANI ALIREZA Sself | 5 | 2012–2014 |
| AGILENT TECHNOLOGIES INC | 1 | 2001 |
| HEWLETT PACKARD CO | 1 | 1998 |
| LEE TED | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 35 | 2002–2019 |
| Toronto, CA | 3 | 1998–2001 |