Inventor

Bruce M. Green

Inventor
Gilbert, AZ, US

Overview

40→
Patents
2005–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 40 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices34%
H01LSemiconductor devices23%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
G06FElectric digital data processing3%
H03KPulse technique3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
10,971,613Semiconductor devices with doped regions functioning as enhanced resistivity regions or diffusion barriers, and methods of fabrication therefor202110,957,790Semiconductor device with selectively etched surface passivation202110,825,924Semiconductor device with selectively etched surface passivation202010,644,142Semiconductor devices with doped regions functioning as enhanced resistivity regions or diffusion barriers, and methods of fabrication therefor202010,541,324Semiconductor device with a recessed ohmic contact and methods of fabrication202010,522,670Semiconductor device with selectively etched surface passivation201910,249,615MISHFET and Schottky device integration201910,128,364Semiconductor devices with an enhanced resistivity region and methods of fabrication therefor201810,074,588Semiconductor devices with a thermally conductive layer and methods of their fabrication201810,033,374Devices with signal and temperature characteristic dependent control circuitry and methods of operation therefor20189,871,107'Device with a conductive feature formed over a cavity and method therefor'20189,825,162'Vertical power transistor device, semiconductor die and method of manufacturing a vertical power transistor device'20179,799,760'Semiconductor device with selectively etched surface passivation'20179,685,345'Semiconductor devices with integrated Schottky diodes and methods of fabrication'20179,660,641'Devices with signal characteristic dependent control circuitry and methods of operation therefor'20179,614,046'Semiconductor devices with a thermally conductive layer'20179,438,224'Devices with signal characteristic dependent control circuitry and methods of operation therefor'20169,362,198'Semiconductor devices with a thermally conductive layer and methods of their fabrication'20169,281,204'Method for improving E-beam lithography gate metal profile for enhanced field control'20169,276,101'High speed gallium nitride transistor devices'20169,153,448'Semiconductor device with selectively etched surface passivation'20159,123,645'Methods of making semiconductor devices with low leakage Schottky contacts'20159,111,868'Semiconductor device with selectively etched surface passivation'20159,099,433'High speed gallium nitride transistor devices'20159,029,986'Transistors with dual layer passivation'20159,024,324'GaN dual field plate device with single field plate metal'20158,946,776'Semiconductor device with selectively etched surface passivation'20158,946,779'MISHFET and Schottky device integration'20158,653,558'Semiconductor device and method of making'20148,609,538'Methods relating to the fabrication of devices having conductive substrate vias with catch-pad etch-stops'20138,592,878'Semiconductor devices with low leakage Schottky contacts'20138,410,580'Device having conductive substrate via with catch-pad etch-stop'20138,304,271'Integrated circuit having a bulk acoustic wave device and a transistor'20128,193,591'Transistor and method with dual layer passivation'20127,935,620'Method for forming semiconductor devices with low leakage Schottky contacts'20117,622,322'Method of forming an AlN coated heterojunction field effect transistor'20097,253,455'pHEMT with barrier optimized for low temperature operation'20077,253,486'Field plate transistor with reduced field plate resistance'20077,229,903'Recessed semiconductor device'20076,867,078'Method for forming a microwave field effect transistor with high operating voltage'2005

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2018Patents assigned to FREESCALE SEMICONDUCTOR INC (27)· patent assignee history
2005–2021Based in Gilbert, AZ, US· patent location history
2012–2019Patents assigned to GREEN BRUCE M (17)· patent assignee history
2013–2017Patents assigned to HILL DARRELL G (7)· patent assignee history
2013–2017Patents assigned to MOORE KAREN E (6)· patent assignee history
2016Based in Gilibert, AZ, US· patent location history
2017–2021Patents assigned to NXP USA INC (16)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FREESCALE SEMICONDUCTOR INC272005–2018
GREEN BRUCE Mself172012–2019
NXP USA INC162017–2021
HILL DARRELL G72013–2017
MOORE KAREN E62013–2017
Locations
LocationPatentsSpan
Gilbert, AZ, US392005–2021
Gilibert, AZ, US12016