Inventor
Thomas Vogelsang
Inventor
Mountain View, CA, US
Overview
Patents· 113 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores26%
H04NPictorial communication, e.g. television16%
G06FElectric digital data processing11%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H03KPulse technique2%
PatentTitleYear
11,114,150Memory system with multiple open rows per bank202111,109,512Memory subsystem for a cryogenic digital system202111,081,1762T-1R architecture for resistive RAM202111,069,392Memory component with efficient write operations202111,032,495Shared-counter image sensor202111,029,216IC with stragically biased digital circuitry202111,012,649Feedthrough-compensated image sensor202111,011,248DRAM retention test method for dynamic error correction202111,004,530Testing through-silicon-vias202110,885,946Stacked DRAM device and method of manufacture202110,860,253Memory component having internal read-modify-write operation202010,839,884Memory component with efficient write operations202010,811,062Deferred fractional memory row activation202010,798,322High dynamic-range image sensor202010,706,913Reduced transport energy in a memory system202010,659,715Fractional-readout oversampled image sensor202010,652,435Methods and systems for reducing image artifacts202010,652,493Low-noise, high dynamic-range image sensor202010,622,0622T-1R architecture for resistive ram202010,614,859Stacked DRAM device and method of manufacture202010,594,973Conditional-reset, multi-bit read-out image sensor202010,497,457DRAM retention test method for dynamic error correction201910,388,337Memory with deferred fractional row activation201910,378,967Dual temperature band integrated circuit device201910,362,256Fractional-readout oversampled image sensor201910,356,350Dark-emulation image sensor201910,274,652Systems and methods for improving resolution in lensless imaging201910,277,843Oversampled image sensor with conditional pixel readout201910,269,411Memory controller and memory device command protocol201910,264,195Shared-counter image sensor201910,261,584Touchless user interface for handheld and wearable computers201910,262,750Testing through-silicon-vias201910,248,358Memory component having internal read-modify-write operation201910,249,660Split-gate conditional-reset image sensor201910,204,662Stacked DRAM device and method of manufacture201910,199,0982T-1R architecture for resistive RAM201910,199,089Reduced transport energy in a memory system201910,178,329Oversampled high dynamic-range image sensor201910,165,209Low-noise, high dynamic-range image sensor201810,154,220Imaging system with dynamic reconstruction workload allocation201810,136,090Threshold-monitoring, conditional-reset image sensor201810,104,318High dynamic-range image sensor201810,070,084Image sensor with multi-range readout201810,037,8012T-1R architecture for resistive RAM20189,983,830Memory component having internal read modify-write operation20189,911,468'Memory with deferred fractional row activation'20189,894,304'Line-interleaved image sensors'20189,875,787Reduced transport energy in a memory system20189,826,176'Shared-counter image sensor'20179,691,504'DRAM retention test method for dynamic error correction'20179,681,071'Image sensor with exception-coded output compression'20179,667,898'Conditional-reset, multi-bit read-out image sensor'20179,666,238'Stacked DRAM device and method of manufacture'20179,575,835'Error correction in a memory device'20179,570,144'Memory refresh method and devices'20179,570,196'Testing through-silicon-vias'20179,570,126'Memory with deferred fractional row activation'20179,548,102'Multi-die DRAM banks arrangement and wiring'20179,521,338'Image sensor sampled at non-uniform intervals'20169,521,349'Image sensor architecture with power saving readout'20169,521,351'Fractional-readout oversampled image sensor'20169,515,008'Techniques for interconnecting stacked dies using connection sites'20169,491,391'Image sensor with threshold-based output encoding'20169,437,280'DRAM sense amplifier that supports low memory-cell capacitance'20169,438,826'Pixel structure and reset scheme'20169,432,597'Low-noise, high dynamic-range image sensor'20169,411,678'DRAM retention monitoring method for dynamic error correction'20169,380,245'Conditional-reset image sensor with analog counter array'20169,361,960'Configurable memory banks of a memory device'20169,344,635'Conditional-reset, temporally oversampled image sensor'20169,330,735'Memory with deferred fractional row activation'20169,287,239'Techniques for interconnecting stacked dies using connection sites'20169,286,965'Memory refresh method and devices'20169,264,639'Feedthrough-compensated image sensor'20169,256,376'Methods and circuits for dynamically scaling DRAM power and performance'20169,214,219'Distributed sub-page selection'20159,116,781'Memory controller and memory device command protocol'20159,111,588'Multi-die DRAM banks arrangement and wiring'20159,036,065'Shared-counter image sensor'20159,037,949'Error correction in a memory device'20159,001,606'Memory methods and systems with adiabatic switching'20159,001,251'Oversampled image sensor with conditional pixel readout'20158,982,598'Stacked memory device with redundant resources to correct defects'20158,930,779'Bit-replacement technique for DRAM error correction'20158,918,702'Semiconductor memory having non-standard form factor'20148,908,454'Memory architecture with redundant resources'20148,885,423'DRAM sense amplifier that supports low memory-cell capacitance'20148,811,095'Methods and circuits for dynamically scaling DRAM power and performance'20148,717,797'Semiconductor memory device with hierarchical bitlines'20148,473,808'Semiconductor memory having non-standard form factor'20137,956,644'Peak power reduction using fixed bit inversion'20117,937,631'Method for self-test and self-repair in a multi-chip package environment'20117,797,511'Memory refresh system and method'20107,440,347'Circuit and method to find wordline-bitline shorts in a DRAM'20087,375,999'Low equalized sense-amp for twin cell DRAMs'20087,342,291'Standby current reduction over a process window with a trimmable well bias'20087,333,383'Fuse resistance read-out circuit'20087,293,190'Noisy clock test method and apparatus'20077,254,089'Memory with selectable single cell or twin cell configuration'20077,227,799'Sense amplifier for eliminating leakage current due to bit line shorts'20077,060,529'Multiple chip semiconductor arrangement having electrical components in separating regions'20067,060,566'Standby current reduction over a process window with a trimmable well bias'20066,815,803'Multiple chip semiconductor arrangement having electrical components in separating regions'20046,813,193'Memory device and method of outputting data from a memory device'20046,730,989'Semiconductor package and method'20046,369,606'Mixed threshold voltage CMOS logic device and method of manufacture therefor'20026,160,747'Configuration for crosstalk attenuation in word lines of DRAM circuits'20006,067,261'Timing of wordline activation for DC burn-in of a DRAM with the self-refresh'20006,049,492'Interleaved sense amplifier with a single-sided precharge device'20005,612,233'Method for manufacturing a single electron component'19975,559,353'Integrated circuit structure having at least one CMOS-NAND gate and method for the manufacture thereof'19965,540,977'Microelectronic component'19965,443,992'Method for manufacturing an integrated circuit having at least one MOS transistor'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2000Patents assigned to SIEMENS AG (6)· patent assignee history
1995–1996Based in Munich, DE· patent location history
1996–1997Based in Essex Junction, VT, US· patent location history
2000Based in Williston, VT, US· patent location history
2002–2011Based in Jericho, VT, US· patent location history
2004–2014Patents assigned to INFINEON TECHNOLOGIES AG (12)· patent assignee history
2013–2017Patents assigned to VOGELSANG THOMAS (15)· patent assignee history
2013–2021Based in Mountain View, CA, US· patent location history
2014–2021Patents assigned to RAMBUS INC (84)· patent assignee history
2018–2021Patents assigned to HEFEI RELIANCE MEMORY LTD (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 84 | 2014–2021 |
| VOGELSANG THOMASself | 15 | 2013–2017 |
| INFINEON TECHNOLOGIES AG | 12 | 2004–2014 |
| SIEMENS AG | 6 | 1995–2000 |
| HEFEI RELIANCE MEMORY LTD | 4 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mountain View, California, US | 90 | 2013–2021 |
| Jericho, VT, US | 15 | 2002–2011 |
| Williston, VT, US | 3 | 2000 |
| Essex Junction, VT, US | 2 | 1996–1997 |
| Munich, DE | 2 | 1995–1996 |