Inventor
MICHAEL J. SEDDON
Inventor
US
Overview
Patents· 75 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H10DInorganic electric semiconductor devices5%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
B23KSoldering or unsoldering2%
B24BMachines, devices, or processes for grinding or polishing2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
G01RMeasuring electric variables1%
PatentTitleYear
12,476,132Curved semiconductor die systems and related methods202512,469,709Semiconductor package electrical contact structures and related methods202512,444,609Silicon-on-insulator die support structures and related methods202512,431,359Semiconductor package electrical contacts and related methods202512,376,333Configurable low ohmic power circuits202512,374,555Die sidewall coatings and related methods202512,374,554Semiconductor packages with die including cavities and related methods202512,354,917Singulation systems and related methods202512,341,069Backside metal patterning die singulation system and related methods202512,322,632Substrate alignment systems and related methods202512,315,765Backside metal patterning die singulation systems and related methods202512,272,572Non-planar semiconductor packaging systems and related methods202512,266,590Dual side direct cooling semiconductor package202512,255,167Semiconductor packages with an intermetallic layer202512,230,559Semiconductor device and method of forming micro interconnect structures202512,230,502Semiconductor package stress balance structures and related methods202512,230,543Die cleaning systems and related methods202512,230,551Immersion direct cooling modules202512,211,784SOI substrate and related methods202512,154,783Semiconductor wafer and method of wafer thinning202412,154,877Semiconductor wafer and method of ball drop on thin wafer with edge support ring202412,148,665Jet ablation die singulation systems and related methods202412,132,005Supports for thinned semiconductor substrates and related methods202412,132,008Multidie supports and related methods202412,119,294Through-substrate via structure and method of manufacture202412,094,750Tape heating methods202412,040,192Die sidewall coatings and related methods202412,040,295Semiconductor device with backmetal and related methods202412,020,972Curved semiconductor die systems and related methods202411,987,874Backside metal formation methods and systems202411,972,980Singulation systems and related methods202411,948,880SOI substrate and related methods202411,942,366Backside metal patterning die singulation systems and related methods202411,929,285Backside metal patterning die singulation system and related methods202411,908,699Semiconductor packages with die including cavities202411,901,184Backmetal removal methods202411,894,245Non-planar semiconductor packaging systems and related methods202411,854,995Supports for thinned semiconductor substrates and related methods202311,854,889Die cleaning systems and related methods202311,830,771Semiconductor substrate production systems and related methods202311,830,756Temporary die support structures and related methods202311,823,965Substrate processing carrier202311,823,953Semiconductor substrate processing methods202311,756,830Jet ablation die singulation systems and related methods202311,710,691Semiconductor device and method of forming micro interconnect structures202311,694,937Semiconductor wafer and method of probe testing202311,676,863Structures for aligning a semiconductor wafer for singulation202311,651,998Plasma die singulation systems and related methods202311,652,010Semiconductor substrate crack mitigation systems and related methods202311,616,008Through-substrate via structure and method of manufacture202311,605,561Backside metal removal die singulation systems and related methods202311,581,223Backside metal patterning die singulation system and related methods202311,508,579Backside metal photolithographic patterning die singulation systems and related methods202211,495,493Backside metal patterning die singulation systems and related methods202211,495,529SOI substrate and related methods202211,437,291Multichip module supports and related methods202211,430,746Multidie supports for reducing die warpage202211,404,277Die sidewall coatings and related methods202211,393,692Semiconductor package electrical contact structures and related methods202211,387,145Jet ablation die singulation systems and related methods202211,387,130Substrate alignment systems and related methods202211,373,859Semiconductor substrate singulation systems and related methods202211,367,619Semiconductor package electrical contacts and related methods202211,361,970Silicon-on-insulator die support structures and related methods202211,348,796Backmetal removal methods202211,342,189Semiconductor packages with die including cavities and related methods202211,289,380Backside metal patterning die singulation systems and related methods202211,289,381Methods of aligning a semiconductor wafer for singulation202211,289,358Wafer thinning systems and related methods202211,254,565Absolute and differential pressure sensors and related methods202211,257,724Semiconductor wafer and method of probe testing202211,222,840Silicon-on-insulator (SOI) substrate and related methods202211,211,359Semiconductor device and method of forming modular 3D semiconductor package with horizontal and vertical oriented substrates202111,164,835Semiconductor wafer and method of ball drop on thin wafer with edge support ring202111,152,211Semiconductor wafer thinning systems and related methods2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to SEMICONDUCTOR COMPONENTS IND LLC (75)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEMICONDUCTOR COMPONENTS IND LLC | 75 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 75 | 2021–2025 |