Inventor
Steven L. Scott
Inventor
Eau Claire, WI, US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing67%
H04LTransmission of digital information, e.g. telegraphic communication30%
H04QSelecting3%
PatentTitleYear
10,860,524Extended fast memory access in a multiprocessor computer system202010,153,985Dragonfly processor interconnect network20189,886,409'System and method for configuring a channel'20189,614,786'Dragonfly processor interconnect network'20179,537,772'Flexible routing tables for a high-radix router'20179,294,551'Collective engine method and apparatus'20169,201,689'Software emulation of massive hardware threading for tolerating remote memory references'20159,069,672'Extended fast memory access in a multiprocessor computer system'20159,058,453'System and method for configuring a channel'20158,792,512'Reliable message transport network'20148,774,203'One-way message notification with out-of-order packet delivery'20148,761,166'Flexible routing tables for a high-radix router'20148,635,172'Dynamic techniques for evaluating quality of clustering or classification system aimed to minimize the number of manual reviews based on Bayesian inference and Markov Chain Monte Carlo (MCMC) techniques'20148,601,236'Configurable vector length computer processor'20138,386,750'Multiprocessor system having processors with different address widths and method for operating the same'20138,380,935'Atomic memory operation cache protocol with opportunistic combining'20138,307,194'Relaxed memory consistency model'20128,261,134'Error management watchdog timers in a multiprocessor computer'20128,239,704'Global clock via embedded spanning tree'20128,223,778'Routing table architecture'20128,184,626'High-radix interprocessor communications system and method'20128,095,759'Error management firewall in a multiprocessor computer'20127,864,792'Load balancing for communications within a multiprocessor computer system'20117,852,836'Reduced arbitration routing system and method'20107,843,929'Flexible routing tables for a high-radix router'20107,830,905'Speculative forwarding in a high-radix router'20107,743,223'Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system'20107,543,133'Latency tolerant distributed shared memory multiprocessor computer'20097,519,771'System and method for processing memory instructions using a forced order queue'20097,437,521'Multistream processing memory-and barrier-synchronization method and apparatus'20087,409,505'Optimized high bandwidth cache coherence mechanism'20087,356,026'Node translation and protection in a clustered multiprocessor system'20087,334,110'Decoupled scalar/vector computer architecture system and method'20087,082,500'Optimized high bandwidth cache coherence mechanism'20066,925,547'Remote address translation in a multiprocessor system'20056,922,766'Remote translation mechanism for a multi-node system'20056,643,764'Multiprocessor system utilizing multiple links to improve point to point bandwidth'20036,633,958'Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure'20036,233,704'System and method for fault-tolerant transmission of data within a dual ring network'20016,216,174'System and method for fast barrier synchronization'20016,085,303'Seralized race-free virtual barrier network'20006,029,212'Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers'20005,958,017'Adaptive congestion control mechanism for modular computer networks'19995,864,738'Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller'19995,841,973'Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue\'s tail pointer structure in local memory'19985,835,925'Using external registers to extend memory reference capabilities of a microprocessor'19985,761,706'Stream buffers for high-performance computer memory system'19985,748,900'Adaptive congestion control mechanism for modular computer networks'19985,701,416'Adaptive routing mechanism for torus interconnection network'19975,659,796'System for randomly modifying virtual channel allocation and accepting the random modification based on the cost function'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2000Patents assigned to CRAY RESEARCH INC (10)· patent assignee history
1997–2018Based in Eau Claire, WI, US· patent location history
2005–2016Patents assigned to CRAY INC (22)· patent assignee history
2010–2020Based in Chippewa Falls, WI, US· patent location history
2012–2015Patents assigned to SCOTT STEVEN L (14)· patent assignee history
2012–2015Patents assigned to ABTS DENNIS C (9)· patent assignee history
2012–2020Patents assigned to INTEL CORP (9)· patent assignee history
2014Based in Mountain View, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CRAY INC | 22 | 2005–2016 |
| SCOTT STEVEN Lself | 14 | 2012–2015 |
| CRAY RESEARCH INC | 10 | 1997–2000 |
| ABTS DENNIS C | 9 | 2012–2015 |
| INTEL CORP | 9 | 2012–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Eau Claire, WI, US | 32 | 1997–2018 |
| Chippewa Falls, WI, US | 17 | 2010–2020 |
| Mountain View, California, US | 1 | 2014 |