Inventor
Bruce Faure
Inventor
Grenoble, FR
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
C30BSingle-crystal growth13%
H10HInorganic light-emitting semiconductor devices having potential barriers8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
H10DInorganic electric semiconductor devices4%
H01LSemiconductor devices4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation4%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution4%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,401,536Item coated with a silicon/organic layer improving the performances of an outer coating20199,242,444'Method of fabricating a composite structure with a stable bonding layer of oxide'20169,041,165'Relaxation and transfer of strained material layers'20159,011,598'Method for making a composite substrate and composite substrate according to the method'20158,912,081'Stiffening layers for the relaxation of strained layers'20148,564,019'Heterostructures comprising crystalline strain relaxation layers'20138,541,290'Optoelectronic substrate and methods of making same'20138,492,244'Methods for relaxation and transfer of strained layers and structures fabricated thereby'20138,486,771'Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same'20138,481,407'Processes for fabricating heterostructures'20138,263,984'Process for making a GaN substrate'20128,216,368'Method of fabricating an epitaxially grown layer'20128,153,500'Method of fabricating an epitaxially grown layer on a composite structure'20128,105,916'Relaxation and transfer of strained layers'20128,093,138'Method of fabricating an epitaxially grown layer'20127,981,767'Methods for relaxation and transfer of strained layers and structures fabricated thereby'20117,939,428'Methods for making substrates and substrates formed therefrom'20117,839,001'Methods for making substrates and substrates formed therefrom'20107,736,935'Passivation of semiconductor structures having strained layers'20107,670,930'Method of detaching a thin film by melting precipitates'20107,646,038'Method of fabricating heteroepitaxial microstructures'20107,615,468'Methods for making substrates and substrates formed therefrom'20097,602,046'Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof'20097,601,217'Method of fabricating an epitaxially grown layer'20097,538,010'Method of fabricating an epitaxially grown layer'20097,537,949'Optoelectronic substrate and methods of making same'20097,375,008'Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof'20087,288,430'Method of fabricating heteroepitaxial microstructures'20077,261,777'Method for fabricating an epitaxial substrate'20077,256,473'Composite structure with high heat dissipation'20077,229,898'Methods for fabricating a germanium on insulator wafer'20077,226,509'Method for fabricating a carrier substrate'20077,135,383'Composite structure with high heat dissipation'20066,946,317'Method of fabricating heteroepitaxial microstructures'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to SOITEC SILICON ON INSULATOR (33)· patent assignee history
2005–2015Based in Grenoble, FR· patent location history
2009Based in Grenbole, FR· patent location history
2010–2016Based in Paris, FR· patent location history
2012–2015Patents assigned to FAURE BRUCE (13)· patent assignee history
2012–2015Patents assigned to LETERTRE FABRICE (5)· patent assignee history
2013Patents assigned to GARDNER NATHAN F (2)· patent assignee history
2013–2015Patents assigned to GUENARD PASCAL (2)· patent assignee history
2019Based in Charenton-le-Pont, FR· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SOITEC SILICON ON INSULATOR | 33 | 2005–2016 |
| FAURE BRUCEself | 13 | 2012–2015 |
| LETERTRE FABRICE | 5 | 2012–2015 |
| GARDNER NATHAN F | 2 | 2013 |
| GUENARD PASCAL | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Grenoble, FR | 23 | 2005–2015 |
| Paris, FR | 9 | 2010–2016 |
| Charenton-le-Pont, FR | 1 | 2019 |
| Grenbole, FR | 1 | 2009 |