Inventor
Gian Sharma
Inventor
Fremont, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices23%
H01LSemiconductor devices21%
H10DInorganic electric semiconductor devices15%
H10NElectric solid-state devices not otherwise provided for15%
G11CStatic stores11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G06FElectric digital data processing1%
H01JElectric discharge tubes or discharge lamps1%
PatentTitleYear
11,086,619Code analytics and publication platform202110,854,260Adjustable current selectors202010,770,510Dual threshold voltage devices having a first transistor and a second transistor202010,770,561Methods of fabricating dual threshold voltage devices202010,614,867Patterning of high density small feature size pillar structures202010,497,415Dual gate memory devices201910,460,778Perpendicular magnetic tunnel junction memory cells having shared source contacts201910,438,999Annular vertical Si etched channel MOS devices201910,355,047Fabrication methods of forming annular vertical SI etched channel MOS devices201910,347,822Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices201910,347,311Cylindrical vertical SI etched channel 3D switching devices201910,319,424Adjustable current selectors201910,192,789Methods of fabricating dual threshold voltage devices201910,192,787Methods of fabricating contacts for cylindrical devices201910,192,984Dual threshold voltage devices with stacked gates201910,192,788Methods of fabricating dual threshold voltage devices with stacked gates201910,186,551Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)20196,969,687'Method of planarizing a semiconductor die'20056,756,284'Method for forming a sublithographic opening in a semiconductor process'20046,703,318'Method of planarizing a semiconductor die'20046,699,772'Hybrid trench isolation technology for high voltage isolation using thin field oxide in a semiconductor process'20044,437,961'Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber'1984Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1984Patents assigned to NASA (1)· patent assignee history
1984Based in Huntsville, AL, US· patent location history
2004–2005Patents assigned to SILICON STORAGE TECH INC (3)· patent assignee history
2004–2005Based in San Jose, CA, US· patent location history
2019–2020Patents assigned to SPIN MEMORY INC (11)· patent assignee history
2019Patents assigned to SPIN TRANSFER TECH (4)· patent assignee history
2019–2020Based in Fremont, CA, US· patent location history
2021Patents assigned to MORGAN STANLEY SERVICES GROUP INC (1)· patent assignee history
2021Based in Pennington, NJ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPIN MEMORY INC | 11 | 2019–2020 |
| SPIN TRANSFER TECH | 4 | 2019 |
| SILICON STORAGE TECH INC | 3 | 2004–2005 |
| MORGAN STANLEY SERVICES GROUP INC | 1 | 2021 |
| NASA | 1 | 1984 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 16 | 2019–2020 |
| San Jose, California, US | 4 | 2004–2005 |
| Pennington, New Jersey, US | 1 | 2021 |
| Huntsville, AL, US | 1 | 1984 |