Inventor
True-Lon Lin
Inventor
Cupertino, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices47%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
B82YSpecific uses or applications of nanostructures6%
G01JMeasurement of intensity, velocity, spectral content, polarisation, phase or pulse characteristics of infrared, visible or ultraviolet light6%
C23FNon-mechanical removal of metallic material from surface3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
6,919,168'Masking methods and etching sequences for patterning electrodes of high density RAM capacitors'20056,734,452'Infrared radiation-detecting device'20046,211,529'Infrared radiation-detecting device'20016,104,060'Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate'20005,986,304'Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners'19995,923,065'Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings'19995,907,169'Self-aligned and process-adjusted high density power transistor with gate sidewalls provided with punch through prevention and reduced JFET resistance'19995,895,951'MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches'19995,883,416'Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage'19995,877,529'Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness'19995,844,277'Power MOSFETs and cell topology'19985,763,915'DMOS transistors having trenched gate oxide'19985,731,611'MOSFET transistor cell manufactured with selectively implanted punch through prevent and threshold reductoin zones'19985,729,037'MOSFET structure and fabrication process for decreasing threshold voltage'19985,668,026'DMOS fabrication process implemented with reduced number of masks'19975,648,297'Long-wavelength PTSI infrared detectors and method of fabrication thereof'19975,075,243'Fabrication of nanometer single crystal metallic CoSi.sub.2 structures on Si'19915,010,037'Pinhole-free growth of epitaxial CoSi.sub.2 film on Si(111)'19914,990,988'Laterally stacked Schottky diodes for infrared sensor applications'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2004Patents assigned to CALIFORNIA INST OF TECHN (3)· patent assignee history
1991Patents assigned to NASA (2)· patent assignee history
1991–1997Based in Cerritos, CA, US· patent location history
1997–2000Patents assigned to MEGAMOS CORP (10)· patent assignee history
1997–2005Based in Cupertino, CA, US· patent location history
1998Patents assigned to MAGEMOS CORP (1)· patent assignee history
2005Patents assigned to APPLIED MATERIALS INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MEGAMOS CORP | 10 | 1997–2000 |
| CALIFORNIA INST OF TECHN | 3 | 1991–2004 |
| NASA | 2 | 1991 |
| APPLIED MATERIALS INC | 1 | 2005 |
| MAGEMOS CORP | 1 | 1998 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 15 | 1997–2005 |
| Cerritos, California, US | 4 | 1991–1997 |