Inventor
Joachim Schnabel
Inventor
Mnchen, DE
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores52%
H03KPulse technique16%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems12%
F42BExplosive charges, e.g. for blasting, fireworks, ammunition4%
H02HEmergency protective circuit arrangements4%
H03MCoding4%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
PatentTitleYear
8,872,689'Circuit arrangement and method for operating an analog-to-digital converter'20147,180,805'Differental current source for generating DRAM refresh signal'20077,136,320'Method and regulating circuit for refreshing dynamic memory cells'20067,068,079'Circuit device with clock pulse detection facility'20067,049,930'Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement'20066,870,420'Method of increasing an internal operating voltage for an integrated circuit, and integrated circuit'20056,850,448'Temperature-dependent refresh cycle for DRAM'20056,850,099'Scalable driver device and related integrated circuit'20056,833,745'Signal generator for charge pump in an integrated circuit'20046,809,980'Limiter for refresh signal period in DRAM'20046,737,895'Control signal generating device for driving a plurality of circuit units'20046,721,214'Drive circuit and control method'20046,700,426'Programmable voltage pump having a ground option'20046,690,605'Logic signal level converter circuit and memory data output buffer using the same'20046,545,930'Integrated memory having a voltage regulating circuit'20036,477,106'Circuit configuration for deactivating word lines in a memory matrix'20026,456,553'Circuit configuration for switching over a receiver circuit in particular in DRAM memories and DRAM memory having the circuit configuration'20026,370,069'Method for testing a multiplicity of word lines of a semiconductor memory configuration'20024,359,957'Torpedo and operating method'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1982Patents assigned to TRW INC (1)· patent assignee history
2002–2014Patents assigned to INFINEON TECHNOLOGIES AG (18)· patent assignee history
2002–2004Based in Mnchen, DE· patent location history
2004–2007Based in Munich, DE· patent location history
2004Based in Berlin, DE· patent location history
2005–2006Based in München, DE· patent location history
2014Based in Villach, AT· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 18 | 2002–2014 |
| TRW INC | 1 | 1982 |
Locations
| Location | Patents | Span |
|---|---|---|
| Mnchen, DE | 7 | 2002–2004 |
| Munich, DE | 6 | 2004–2007 |
| München, DE | 3 | 2005–2006 |
| Villach, AT | 1 | 2014 |
| Berlin, DE | 1 | 2004 |