Inventor
Maheswaran Surendra
Inventor
Croton-on-Hudson, NY, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices13%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes10%
H04LTransmission of digital information, e.g. telegraphic communication8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G05BControl or regulating systems in general7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
9,577,951'Orchestrated peer-to-peer server provisioning'20179,250,972'Orchestrated peer-to-peer server provisioning'20169,195,558'Piloting in service delivery'20158,631,389'Methods and apparatus for authentication of configuration items via configuration item change analysis'20148,600,847'Optimal service fee discount management'20138,473,603'Cross-tier management in multi-tier computing system architecture'20138,386,995'Managing computing deployment in presence of variable workload'20138,347,289'Method and apparatus for online sample interval determination'20138,181,230'System and method for adaptive approximating of a user for role authorization in a hierarchical inter-organizational model'20128,122,450'Method and apparatus for distributing memory in a data processing system'20127,987,146'System and method for matching multi-node software system provisioning requirements and capabilities using rough set theory'20117,953,729'Resource optimizations in computing utilities'20117,923,786'Selective silicon-on-insulator isolation structure and method'20117,913,227'Methods and apparatus for management of configuration item lifecycle state transitions'20117,822,785'Methods and apparatus for composite configuration item management in configuration management database'20107,716,016'Method and apparatus for automatic uncertainty-based management feedback controller'20107,707,345'Methods and apparatus for managing deadtime in feedback control queuing system'20107,565,655'Methods and systems for control discovery in computing systems'20097,496,564'Resource optimizations in computing utilities'20097,393,776'Method of forming closed air gap interconnects and structures formed thereby'20087,361,991'Closed air gap interconnect structure'20087,350,186'Methods and apparatus for managing computing deployment in presence of variable workload'20087,346,401'Systems and methods for providing constrained optimization using adaptive regulatory control'20087,326,983'Selective silicon-on-insulator isolation structure and method'20087,309,649'Method of forming closed air gap interconnects and structures formed thereby'20077,243,169'Method, system and program for oscillation control of an internal process of a computer program'20077,056,782'CMOS silicide metal gate integration'20067,039,559'Methods and apparatus for performing adaptive and robust prediction'20066,936,522'Selective silicon-on-insulator isolation structure and method'20056,869,899'Lateral-only photoresist trimming for sub-80 nm gate stack'20056,864,041'Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching'20056,743,686'Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication'20046,732,908'High density raised stud microjoining system and methods of fabricating the same'20046,678,569'User configurable multivariate time series reduction tool control method'20046,584,368'User configurable multivariate time series reduction tool control method'20036,528,363'Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch'20036,521,383'Pattern density tailoring for etching of advanced lithographic masks'20036,518,136'Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication'20036,442,445'User configurable multivariate time series reduction tool control method'20026,365,326'Pattern density tailoring for etching of advanced lithographic mask'20025,716,486'Method and apparatus for tuning field for plasma processing using corrected electrode'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2017Based in Croton-on-Hudson, NY, US· patent location history
2002–2017Patents assigned to IBM (39)· patent assignee history
2012–2016Patents assigned to SURENDRA MAHESWARAN (8)· patent assignee history
2012–2013Patents assigned to DIAO YIXIN (3)· patent assignee history
2012–2016Patents assigned to GRABARNIK GENADY (2)· patent assignee history
2013Patents assigned to HELLERSTEIN JOSEPH L (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 39 | 2002–2017 |
| SURENDRA MAHESWARANself | 8 | 2012–2016 |
| DIAO YIXIN | 3 | 2012–2013 |
| GRABARNIK GENADY | 2 | 2012–2016 |
| HELLERSTEIN JOSEPH L | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Croton-on-Hudson, New York, US | 41 | 1998–2017 |