Inventor
Taranjit Singh Kukal
Inventor
Delhi, IN
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing81%
H05KPrinted circuits12%
G05BControl or regulating systems in general2%
G06TImage data processing or generation, in general2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,997,332System and method for computing electrical over-stress of devices associated with an electronic design202110,783,307System and method for power-grid aware simulation of an IC-package schematic202010,726,188Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface202010,678,978Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view202010,643,020System and method to estimate a number of layers needed for routing a multi-die package202010,558,780Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design202010,528,688System and method for schematic-driven generation of input/output models202010,467,370Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design201910,289,793System and method to generate schematics from layout-fabrics with a common cross-fabric model201910,285,276Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell20199,934,354Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design20189,928,318'System and method for simulating channels'20189,881,119'Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics'20189,881,120'Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness'20189,798,848'Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface'20179,785,141'Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs'20179,454,634'Methods, systems, and computer program product for an integrated circuit package design estimator'20169,449,130'Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs'20169,361,415'Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics'20169,348,960'Method, system, and computer program product for probing or netlisting a multi-fabric electronic design spanning across multiple design fabrics'20169,286,421'Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs'20169,280,621'Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics'20169,223,915'Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics'20158,898,039'Physical topology-driven logical design flow'20148,732,651'Logical design flow with structural compatability verification'20148,656,329'System and method for implementing power integrity topology adapted for parametrically integrated environment'20148,645,894'Configuration and analysis of design variants of multi-domain circuits'20148,566,767'System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation'20138,521,483'Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation'20138,452,582'System and method for adapting behavioral models to fluctuations in parametrically integrated environment'20138,316,342'Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout'20128,286,110'System and method for adapting electrical integrity analysis to parametrically integrated environment'20128,145,458'Method and system for automatic stress analysis of analog components in digital electronic circuit'20127,490,309'Method and system for automatically optimizing physical implementation of an electronic circuit responsive to simulation analysis'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2021Patents assigned to CADENCE DESIGN SYSTEMS INC (34)· patent assignee history
2009–2021Based in Delhi, IN· patent location history
2012–2014Patents assigned to KUKAL TARANJIT SINGH (7)· patent assignee history
2012–2014Patents assigned to AL-HAWARI FERAS (3)· patent assignee history
2012–2014Patents assigned to KOMOW RAYMOND (3)· patent assignee history
2012–2013Patents assigned to KUKAL TARANJIT (3)· patent assignee history
2018Based in Nirankari Colony, IN· patent location history
2019–2020Based in New Delhi, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CADENCE DESIGN SYSTEMS INC | 34 | 2009–2021 |
| KUKAL TARANJIT SINGHself | 7 | 2012–2014 |
| AL-HAWARI FERAS | 3 | 2012–2014 |
| KOMOW RAYMOND | 3 | 2012–2014 |
| KUKAL TARANJITself | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Delhi, IN | 29 | 2009–2021 |
| New Delhi, IN | 4 | 2019–2020 |
| Nirankari Colony, IN | 1 | 2018 |