Inventor
James R. Todd
Inventor
Plano, TX, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices43%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H01LSemiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10BElectronic memory devices2%
PatentTitleYear
10,879,387Drain centered LDMOS transistor with integrated dummy patterns202010,861,948Drift region implant self-aligned to field relief oxide with sidewall dielectric202010,748,818Dynamic biasing to mitigate electrical stress in integrated resistors202010,497,787Drift region implant self-aligned to field relief oxide with sidewall dielectric201910,461,182Drain centered LDMOS transistor with integrated dummy patterns201910,096,685Drift region implant self-aligned to field relief oxide with sidewall dielectric20189,887,288'LDMOS device with body diffusion self-aligned to gate'20189,698,246'LDMOS device with graded body doping'20179,583,612'Drift region implant self-aligned to field relief oxide with sidewall dielectric'20179,461,046'LDMOS device with graded body doping'20168,134,212'Implanted well breakdown in high voltage devices'20127,618,870'Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof'20097,498,652'Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof'20097,262,471'Drain extended PMOS transistor with increased breakdown voltage'20077,208,364'Methods of fabricating high voltage devices'20077,112,480'Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices'20067,005,354'Depletion drain-extended MOS transistors and methods for making the same'20066,969,901'Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices'20056,803,282'Methods for fabricating low CHC degradation mosfet transistors'20046,025,231'Self aligned DMOS transistor and method of fabrication'20005,719,423'Isolated power transistor'19985,539,237'Schottky diode with guard ring'19965,418,185'Method of making schottky diode with guard ring'19955,296,393'Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods'19945,272,098'Vertical and lateral insulated-gate, field-effect transistors, systems and methods'19935,119,162'Integrated power DMOS circuit with protection diode'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2020Patents assigned to TEXAS INSTRUMENTS INC (26)· patent assignee history
1992–2020Based in Plano, TX, US· patent location history
2012Patents assigned to HAO PINGHAI (1)· patent assignee history
2012Patents assigned to SRIDHAR SEETHARAMAN (1)· patent assignee history
2012Patents assigned to TODD JAMES ROBERT (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TEXAS INSTRUMENTS INC | 26 | 1992–2020 |
| HAO PINGHAI | 1 | 2012 |
| SRIDHAR SEETHARAMAN | 1 | 2012 |
| TODD JAMES ROBERTself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Plano, Texas, US | 26 | 1992–2020 |