Inventor
Yasuko Eckert
Inventor
Kirkland, WA, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing48%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use22%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
G11CStatic stores6%
G05FSystems for regulating electric or magnetic variables2%
G06NComputing arrangements based on specific computational models2%
G06TImage data processing or generation, in general2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
11,068,458Mechanism for distributed-system-aware difference encoding/decoding in graph analytics202110,984,838Interconnect architecture for three-dimensional processing systems202110,970,120Method and system for opportunistic load balancing in neural networks using metadata202110,938,709Mechanism for dynamic latency-bandwidth trade-off for efficient broadcasts/multicasts202110,853,904Hierarchical register file at a graphics processing unit202010,838,864Prioritizing local and remote memory access in a non-uniform memory access architecture202010,719,441Using predictions of outcomes of cache memory access requests for controlling whether a request generator sends memory access requests to a memory in parallel with cache memory access requests202010,705,958Coherency directory entry allocation based on eviction costs202010,635,588Distributed coherence directory subsystem with exclusive data regions202010,503,640Selective data retrieval based on access latency201910,452,437Temperature-aware task scheduling and proactive power management201910,389,251Setting operating points for circuits in an integrated circuit chip201910,339,067Mechanism for reducing page migration overhead in memory systems201910,310,981Method and apparatus for performing memory prefetching201910,303,602Preemptive cache management policies for processing units201910,282,295Reducing cache footprint in cache coherence directory201910,198,369Dynamic memory remapping to reduce row-buffer conflicts201910,162,757Proactive cache coherence201810,133,678Method and apparatus for memory management201810,097,091Setting operating points for circuits in an integrated circuit chip20189,947,386Thermal aware data placement and compute dispatch in a memory system20189,921,635'Dynamic and adaptive sleep state management'20189,916,265'Traffic rate control for inter-class data migration in a multiclass memory system'20189,851,777Power gating based on cache dirtiness20179,818,455'Query operations for stacked-die memory device'20179,766,936'Selecting a resource from a set of resources for performing an operation'20179,746,908'Pruning of low power state information for a processor'20179,734,059'Methods and apparatus for data cache way prediction based on classification as stack data'20179,710,392'Virtual memory mapping for improved DRAM page locality'20179,672,161'Configuring a cache management mechanism based on future accesses in a cache'20179,658,663'Thermally-aware throttling in a three-dimensional processor stack'20179,529,718'Batching modified blocks to the same dram page'20169,524,164'Specialized memory disambiguation mechanisms for different memory read access types'20169,507,410'Decoupled selective implementation of entry and exit prediction for power gating processor components'20169,442,557'Using a linear prediction to configure an idle state of an entity in a computing device'20169,443,561'Ring networks for intra- and inter-memory I/O including 3D-stacked memories'20169,378,153'Early write-back of modified data in a cache memory'20169,372,803'Method and system for shutting down active core based caches'20169,367,455'Using predictions for store-to-load forwarding'20169,298,615'Methods and apparatus for soft-partitioning of a data cache for stack data'20169,286,948'Query operations for stacked-die memory device'20169,251,081'Management of caches'20169,251,069'Mechanisms to bound the presence of cache blocks with specific properties in caches'20169,189,399'Stack cache management and coherence techniques'20159,183,055'Selecting a resource from a set of resources for performing an operation'20159,128,856'Selective cache fills in response to write misses'20159,110,671'Idle phase exit prediction'20159,075,730'Mechanisms to bound the presence of cache blocks with specific properties in caches'20158,935,472'Processing device with independently activatable working memory bank and methods'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to ADVANCED MICRO DEVICES INC (49)· patent assignee history
2015–2018Based in Kirkland, WA, US· patent location history
2016Based in Sunnyvale, CA, US· patent location history
2017–2021Based in Bellevue, WA, US· patent location history
2018–2020Based in Redmond, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 49 | 2015–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kirkland, Washington, US | 25 | 2015–2018 |
| Bellevue, Washington, US | 17 | 2017–2021 |
| Redmond, Washington, US | 6 | 2018–2020 |
| Sunnyvale, California, US | 1 | 2016 |