Inventor
SHIH-CHENG CHEN
Inventor
TW
Overview
Patents· 77 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices25%
B82YSpecific uses or applications of nanostructures21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G06FElectric digital data processing2%
G06VImage or video recognition or understanding2%
H04NPictorial communication, e.g. television1%
PatentTitleYear
12,588,247Spacer structures for nano-sheet-based devices202612,557,632Method for fabricating an interconnect structure202612,543,352Integrated circuit with bottom dielectric insulators and fin sidewall spacers for reducing source/drain leakage currents202612,538,570Reduction of gate-drain capacitance202612,532,492Structure and formation method of semiconductor device with epitaxial structures202612,520,543Semiconductor device structure and method for forming the same202612,513,937Semiconductor devices and methods of fabrication thereof202512,513,931Multi-gate device and related methods202512,507,445—202512,484,246Method of manufacturing a semiconductor device including forming a sidewall spacer on a sidewall of a channel structure202512,457,798Dielectric liner for field effect transistors202512,446,319Semiconductor device structure and methods of forming the same202512,446,305Uniform gate width for nanostructure devices202512,439,638FET with wrap-around silicide and fabrication methods thereof202512,438,092Semiconductor device having contact plug connected to gate structure on PMOS region202512,412,775Isolation structures in semiconductor devices202512,349,379Semiconductor devices and methods of manufacture202512,347,775Semiconductor devices with backside power rail and methods of fabrication thereof202512,342,587Integrated circuit with nanostructure transistors and bottom dielectric insulators202512,342,616Semiconductor device structure and methods of forming the same202512,336,240Transistor including dielectric barrier and manufacturing method thereof202512,336,226Semiconductor device structure including stacked nanostructures202512,317,540Method for manufacturing semiconductor structure with isolation feature202512,300,732Gate all around transistor with dual inner spacers202512,272,732Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof202512,272,690Gate isolation for multigate device202512,218,210Semiconductor device202512,205,998Semiconductor device with wrap around silicide and hybrid fin202512,119,270Hybrid source drain regions formed based on same fin and methods forming same202412,107,169Contact structure for stacked multi-gate device202412,087,079Display apparatus and fingerprint sensing method thereof202412,074,204Semiconductor structure and method for forming the same202412,062,721Latch-up prevention202412,057,401Semiconductor device having contact plug connected to gate structure on PMOS region202412,051,736Field effect transistor with inner spacer liner layer and method202412,009,216Methods of forming silicide contact in field-effect transistors202412,009,215Semiconductor device structure with silicide layer202411,996,482Semiconductor device202411,996,483FET with wrap-around silicide and fabrication methods thereof202411,984,363Dual silicide structure and methods thereof202411,967,594Semiconductor device structure and methods of forming the same202411,929,287Dielectric liner for field effect transistors202411,916,122Gate all around transistor with dual inner spacers202411,901,424Semiconductor device202411,901,364Semiconductor device structure and methods of forming the same202411,893,182Electronic device and method for performing fingerprint sensing control202411,854,293Display apparatus and fingerprint sensing method thereof202311,855,096Uniform gate width for nanostructure devices202311,855,216Inner spacers for gate-all-around transistors202311,791,413Semiconductor device and fabrication method thereof202311,791,401Multi-gate device and related methods202311,764,065Methods of forming silicide contact in field-effect transistors202311,756,888Semiconductor device having contact plug connected to gate structure on PMOS region202311,710,774Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof202311,699,760Contact structure for stacked multi-gate device202311,695,076FET with wrap-around silicide and fabrication methods thereof202311,664,230Semiconductor device structure with silicide202311,616,062Gate isolation for multigate device202311,605,737Semiconductor device and manufacturing method thereof202311,532,626Reduction of gate-drain capacitance202211,515,216Dual silicide structure and methods thereof202211,507,225Electronic device, fingerprint sensing control method and fingerprint scanning control method202211,502,034Semiconductor devices with backside power rail and methods of fabrication thereof202211,469,326Semiconductor devices and methods of fabrication thereof202211,450,754Semiconductor devices and methods of manufacture202211,450,663Semiconductor device structure and methods of forming the same202211,430,892Inner spacers for gate-all-around transistors202211,398,550Semiconductor device with facet S/D feature and methods of forming the same202211,380,768Semiconductor device and manufacturing method thereof202211,321,958Electronic device and fingerprint sensing control method thereof202211,315,925Uniform gate width for nanostructure devices202211,309,424Semiconductor device and manufacturing method thereof202211,309,187Methods of forming silicide contact in field-effect transistors202211,264,502Semiconductor device and method202211,245,036Latch-up prevention202211,211,472Semiconductor device and method of forming the same202111,139,379Semiconductor structure and method for forming the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (67)· patent assignee history
2021–2026Based in TW· patent location history
2022–2024Patents assigned to NOVATEK MICROELECTRONICS CORP (5)· patent assignee history
2023–2026Patents assigned to UNITED MICROELECTRONICS CORP (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 67 | 2021–2026 |
| NOVATEK MICROELECTRONICS CORP | 5 | 2022–2024 |
| UNITED MICROELECTRONICS CORP | 5 | 2023–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 77 | 2021–2026 |