Inventor
Takahiro Onodera
Inventor
Tokyo, JP
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1026%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
B24BMachines, devices, or processes for grinding or polishing17%
G06FElectric digital data processing9%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G06TImage data processing or generation, in general4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
H05KPrinted circuits4%
PatentTitleYear
9,880,589'Instrument eject system'20188,492,266'Semiconductor device having insulating film with surface modification layer and method for manufacturing the same'20138,198,730'Semiconductor device and method of manufacturing the same'20128,080,878'Semiconductor device having insulating film with surface modification layer and method for manufacturing the same'20116,995,869'Image processing device and method for generating changes in the light and shade pattern of an image'20066,861,759'Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same'20056,652,354'Polishing apparatus and method with constant polishing pressure'20036,425,801'Polishing process monitoring method and apparatus, its endpoint detection method, and polishing machine using same'20026,270,392'Polishing apparatus and method with constant polishing pressure'20016,165,056'Polishing machine for flattening substrate surface'20005,724,057'Method and apparatus for driving a liquid crystal display'19985,717,251'Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance'19985,640,544'Computer network having an asynchronous document data management system'19975,587,557'Printed circuit board and liquid crystal display'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–1998Patents assigned to IBM (2)· patent assignee history
1996–2018Based in Sagamihara, JP· patent location history
1997–2012Patents assigned to NEC CORP (7)· patent assignee history
1997–2012Based in Tokyo, JP· patent location history
2005–2013Based in Kanagawa, JP· patent location history
2006Based in Saitama, JP· patent location history
2011–2013Patents assigned to HAYASHI YOSHIHIRO (3)· patent assignee history
2011–2013Patents assigned to ONODERA TAKAHIRO (3)· patent assignee history
2011–2013Patents assigned to UEKI MAKOTO (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 7 | 1997–2012 |
| HAYASHI YOSHIHIRO | 3 | 2011–2013 |
| ONODERA TAKAHIROself | 3 | 2011–2013 |
| UEKI MAKOTO | 3 | 2011–2013 |
| IBM | 2 | 1996–1998 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 7 | 1997–2012 |
| Sagamihara, JP | 3 | 1996–2018 |
| Kanagawa, JP | 3 | 2005–2013 |
| Saitama, JP | 1 | 2006 |