Inventor
Suresh K. Venkumahanti
Inventor
Austin, TX, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing69%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
G11CStatic stores5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
B60WConjoint control of vehicle sub-units of different type or different function2%
G01RMeasuring electric variables2%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
11,074,076Dynamic load balancing of hardware threads in clustered processor cores using shared hardware resources, and related circuits, methods, and computer-readable media202110,719,325System and method of VLIW instruction processing using reduced-width VLIW processor202010,625,752System and method for online functional testing for error-correcting code function202010,353,447Current in-rush mitigation for power-up of embedded memories201910,068,645Multiple cycle search content addressable memory201810,055,227Using the least significant bits of a called function's address to switch processor modes201810,025,711Hybrid write-through/write-back cache policy managers, and related systems and methods201810,007,613Reconfigurable fetch pipeline20189,928,159'System and method to select a packet format based on a number of executed threads'20189,824,013'Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors'20179,804,969'Speculative addressing using a virtual address-to-physical address page crossing buffer'20179,715,392'Multiple clustered very long instruction word processing core'20179,678,758'Coprocessor for out-of-order loads'20179,678,754'System and method of processing hierarchical very long instruction packets'20179,552,033'Latency-based power mode units for controlling power modes of processor cores, and related methods and systems'20179,529,727'Reconfigurable fetch pipeline'20169,489,204'Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process'20169,384,825'Multi-port memory circuits'20169,367,468'Data cache way prediction'20169,361,109'System and method to evaluate a data value as an instruction'20169,304,932'Instruction cache having a multi-bit way prediction mask'20169,208,102'Overlap checking for a translation lookaside buffer (TLB)'20159,122,486'Bimodal branch predictor encoded in a branch instruction'20159,116,685'Table call instruction for frequently called functions'20158,990,543'System and method for generating and using predicates within a single instruction packet'20158,972,642'Low latency two-level interrupt controller interface to multi-threaded processor'20158,880,958'Interleaved architecture tracing and microarchitecture tracing'20148,874,884'Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold'20148,868,888'System and method of executing instructions in a multi-stage data processing pipeline'20148,843,730'Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination'20148,725,991'Register file system and method for pipelined processing'20148,578,382'Associating data for events occurring in software threads with synchronized clock cycle counters'20138,533,530'Method and system for trusted/untrusted digital signal processor debugging operations'20138,397,238'Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor'20138,380,966'Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging'20138,370,806'Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor'20138,341,604'Embedded trace macrocell for enhanced digital signal processor debugging operations'20128,341,353'System and method to access a portion of a level two memory and a level one memory'20128,145,874'System and method of data forwarding within an execution unit'20128,140,823'Multithreaded processor with lock indicator'20127,984,281'Shared interrupt controller for a multi-threaded processor'20117,979,681'System and method of selectively accessing a register file'20117,941,646'Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor'20117,827,356'System and method of using an N-way cache'20107,657,791'Method and system for a digital signal processor debugging during power transitions'20106,785,772'Data prefetching apparatus in a data processing system and method therefor'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Based in Austin, TX, US· patent location history
2010–2020Patents assigned to QUALCOMM INC (43)· patent assignee history
2012–2018Patents assigned to CODRESCU LUCIAN (19)· patent assignee history
2012–2018Patents assigned to VENKUMAHANTI SURESH K (13)· patent assignee history
2012–2016Patents assigned to VENKUMAHANTI SURESH (9)· patent assignee history
2012–2017Patents assigned to PLONDKE ERICH JAMES (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 43 | 2010–2020 |
| CODRESCU LUCIAN | 19 | 2012–2018 |
| VENKUMAHANTI SURESH Kself | 13 | 2012–2018 |
| VENKUMAHANTI SURESHself | 9 | 2012–2016 |
| PLONDKE ERICH JAMES | 6 | 2012–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 46 | 2004–2021 |